1/*
2 * Copyright (c) 2021 Argentum Systems Ltd.
3 * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <atmel/saml2x.dtsi>
9
10/ {
11	aliases {
12		tcc-0 = &tcc0;
13		tcc-1 = &tcc1;
14		tcc-2 = &tcc2;
15	};
16
17	soc {
18		tcc0: tcc@42001400 {
19			compatible = "atmel,sam0-tcc";
20			reg = <0x42001400 0x80>;
21			interrupts = <14 0>;
22			clocks = <&gclk 25>, <&mclk 0x1c 5>;
23			clock-names = "GCLK", "MCLK";
24			status = "disabled";
25
26			channels = <4>;
27			counter-size = <24>;
28		};
29
30		tcc1: tcc@42001800 {
31			compatible = "atmel,sam0-tcc";
32			reg = <0x42001800 0x80>;
33			interrupts = <15 0>;
34			clocks = <&gclk 25>, <&mclk 0x1c 6>;
35			clock-names = "GCLK", "MCLK";
36			status = "disabled";
37
38			channels = <4>;
39			counter-size = <24>;
40		};
41
42		tcc2: tcc@42001c00 {
43			compatible = "atmel,sam0-tcc";
44			reg = <0x42001C00 0x80>;
45			interrupts = <16 0>;
46			clocks = <&gclk 26>, <&mclk 0x1c 7>;
47			clock-names = "GCLK", "MCLK";
48			status = "disabled";
49
50			channels = <2>;
51			counter-size = <16>;
52		};
53	};
54};
55
56&dac {
57	interrupts = <24 0>;
58	clocks = <&gclk 32>, <&mclk 0x1c 12>;
59	clock-names = "GCLK", "MCLK";
60};
61
62&sercom0 {
63	interrupts = <8 0>;
64	clocks = <&gclk 18>, <&mclk 0x1c 0>;
65	clock-names = "GCLK", "MCLK";
66};
67
68&sercom1 {
69	interrupts = <9 0>;
70	clocks = <&gclk 19>, <&mclk 0x1c 1>;
71	clock-names = "GCLK", "MCLK";
72};
73
74&sercom2 {
75	interrupts = <10 0>;
76	clocks = <&gclk 20>, <&mclk 0x1c 2>;
77	clock-names = "GCLK", "MCLK";
78};
79
80&sercom3 {
81	interrupts = <11 0>;
82	clocks = <&gclk 21>, <&mclk 0x1c 3>;
83	clock-names = "GCLK", "MCLK";
84};
85
86&sercom4 {
87	interrupts = <12 0>;
88	clocks = <&gclk 22>, <&mclk 0x1c 4>;
89	clock-names = "GCLK", "MCLK";
90};
91
92&sercom5 {
93	interrupts = <13 0>;
94	clocks = <&gclk 24>, <&mclk 0x20 1>;
95	clock-names = "GCLK", "MCLK";
96};
97
98&tc4 {
99	interrupts = <21 0>;
100	clocks = <&gclk 29>, <&mclk 0x20 2>;
101	clock-names = "GCLK", "MCLK";
102};
103
104&adc {
105	interrupts = <22 0>;
106	interrupt-names = "resrdy";
107	clocks = <&gclk 30>, <&mclk 0x20 3>;
108	clock-names = "GCLK", "MCLK";
109};
110