Lines Matching +full:counter +full:- +full:size
6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32f7_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32f4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h>
18 #include <zephyr/dt-bindings/adc/adc.h>
19 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
20 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
21 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
27 zephyr,flash-controller = &flash;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 compatible = "arm,cortex-m7";
38 #address-cells = <1>;
39 #size-cells = <1>;
42 compatible = "arm,armv7m-mpu";
48 quadspi_memory: memory-placeholder@90000000 {
49 compatible = "zephyr,memory-region", "mmio-sram";
51 zephyr,memory-region = "QSPI_PLACEHOLDER";
52 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>;
56 clk_hse: clk-hse {
57 #clock-cells = <0>;
58 compatible = "st,stm32-hse-clock";
62 clk_hsi: clk-hsi {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <DT_FREQ_M(16)>;
69 clk_lse: clk-lse {
70 #clock-cells = <0>;
71 compatible = "st,stm32-lse-clock";
72 clock-frequency = <32768>;
73 driving-capability = <0>;
77 clk_lsi: clk-lsi {
78 #clock-cells = <0>;
79 compatible = "fixed-clock";
80 clock-frequency = <DT_FREQ_K(32)>;
85 #clock-cells = <0>;
86 compatible = "st,stm32f7-pll-clock";
93 compatible = "st,stm32-clock-mco";
98 compatible = "st,stm32-clock-mco";
104 fmc: memory-controller@a0000000 {
105 compatible = "st,stm32-fmc";
111 compatible = "st,stm32-fmc-sdram";
112 #address-cells = <1>;
113 #size-cells = <0>;
118 flash: flash-controller@40023c00 {
119 compatible = "st,stm32-flash-controller", "st,stm32f7-flash-controller";
123 #address-cells = <1>;
124 #size-cells = <1>;
127 compatible = "st,stm32-nv-flash", "soc-nv-flash";
129 write-block-size = <1>;
131 max-erase-time = <4000>;
136 compatible = "st,stm32-rcc";
137 #clock-cells = <2>;
140 rctl: reset-controller {
141 compatible = "st,stm32-rcc-rctl";
142 #reset-cells = <1>;
146 exti: interrupt-controller@40013c00 {
147 compatible = "st,stm32-exti";
148 interrupt-controller;
149 #interrupt-cells = <1>;
150 #address-cells = <1>;
152 num-lines = <16>;
155 interrupt-names = "line0", "line1", "line2", "line3",
156 "line4", "line5-9", "line10-15";
157 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
161 pinctrl: pin-controller@40020000 {
162 compatible = "st,stm32-pinctrl";
163 #address-cells = <1>;
164 #size-cells = <1>;
168 compatible = "st,stm32-gpio";
169 gpio-controller;
170 #gpio-cells = <2>;
176 compatible = "st,stm32-gpio";
177 gpio-controller;
178 #gpio-cells = <2>;
184 compatible = "st,stm32-gpio";
185 gpio-controller;
186 #gpio-cells = <2>;
192 compatible = "st,stm32-gpio";
193 gpio-controller;
194 #gpio-cells = <2>;
200 compatible = "st,stm32-gpio";
201 gpio-controller;
202 #gpio-cells = <2>;
208 compatible = "st,stm32-gpio";
209 gpio-controller;
210 #gpio-cells = <2>;
216 compatible = "st,stm32-gpio";
217 gpio-controller;
218 #gpio-cells = <2>;
224 compatible = "st,stm32-gpio";
225 gpio-controller;
226 #gpio-cells = <2>;
232 compatible = "st,stm32-gpio";
233 gpio-controller;
234 #gpio-cells = <2>;
241 compatible = "st,stm32-watchdog";
247 compatible = "st,stm32-window-watchdog";
255 compatible = "st,stm32-usart", "st,stm32-uart";
264 compatible = "st,stm32-usart", "st,stm32-uart";
273 compatible = "st,stm32-usart", "st,stm32-uart";
282 compatible ="st,stm32-uart";
291 compatible = "st,stm32-uart";
300 compatible = "st,stm32-usart", "st,stm32-uart";
309 compatible = "st,stm32-uart";
318 compatible = "st,stm32-uart";
327 compatible = "st,stm32-i2c-v2";
328 clock-frequency = <I2C_BITRATE_STANDARD>;
329 #address-cells = <1>;
330 #size-cells = <0>;
334 interrupt-names = "event", "error";
339 compatible = "st,stm32-i2c-v2";
340 clock-frequency = <I2C_BITRATE_STANDARD>;
341 #address-cells = <1>;
342 #size-cells = <0>;
346 interrupt-names = "event", "error";
351 compatible = "st,stm32-i2c-v2";
352 clock-frequency = <I2C_BITRATE_STANDARD>;
353 #address-cells = <1>;
354 #size-cells = <0>;
358 interrupt-names = "event", "error";
363 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
364 #address-cells = <1>;
365 #size-cells = <0>;
373 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
374 #address-cells = <1>;
375 #size-cells = <0>;
383 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
384 #address-cells = <1>;
385 #size-cells = <0>;
393 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
394 #address-cells = <1>;
395 #size-cells = <0>;
403 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
404 #address-cells = <1>;
405 #size-cells = <0>;
413 compatible = "st,stm32-bxcan";
416 interrupt-names = "TX", "RX0", "RX1", "SCE";
422 compatible = "st,stm32-timers";
427 interrupt-names = "brk", "up", "trgcom", "cc";
432 compatible = "st,stm32-pwm";
434 #pwm-cells = <3>;
439 compatible = "st,stm32-timers";
444 interrupt-names = "global";
449 compatible = "st,stm32-pwm";
451 #pwm-cells = <3>;
454 counter {
455 compatible = "st,stm32-counter";
461 compatible = "st,stm32-timers";
466 interrupt-names = "global";
471 compatible = "st,stm32-pwm";
473 #pwm-cells = <3>;
476 counter {
477 compatible = "st,stm32-counter";
483 compatible = "st,stm32-timers";
488 interrupt-names = "global";
493 compatible = "st,stm32-pwm";
495 #pwm-cells = <3>;
498 counter {
499 compatible = "st,stm32-counter";
505 compatible = "st,stm32-timers";
510 interrupt-names = "global";
515 compatible = "st,stm32-pwm";
517 #pwm-cells = <3>;
520 counter {
521 compatible = "st,stm32-counter";
527 compatible = "st,stm32-timers";
532 interrupt-names = "global";
536 counter {
537 compatible = "st,stm32-counter";
543 compatible = "st,stm32-timers";
548 interrupt-names = "global";
552 counter {
553 compatible = "st,stm32-counter";
559 compatible = "st,stm32-timers";
564 interrupt-names = "brk", "up", "trgcom", "cc";
569 compatible = "st,stm32-pwm";
571 #pwm-cells = <3>;
576 compatible = "st,stm32-timers";
581 interrupt-names = "global";
586 compatible = "st,stm32-pwm";
588 #pwm-cells = <3>;
591 counter {
592 compatible = "st,stm32-counter";
598 compatible = "st,stm32-timers";
603 interrupt-names = "global";
608 compatible = "st,stm32-pwm";
610 #pwm-cells = <3>;
613 counter {
614 compatible = "st,stm32-counter";
620 compatible = "st,stm32-timers";
625 interrupt-names = "global";
630 compatible = "st,stm32-pwm";
632 #pwm-cells = <3>;
635 counter {
636 compatible = "st,stm32-counter";
642 compatible = "st,stm32-timers";
647 interrupt-names = "global";
652 compatible = "st,stm32-pwm";
654 #pwm-cells = <3>;
657 counter {
658 compatible = "st,stm32-counter";
664 compatible = "st,stm32-timers";
669 interrupt-names = "global";
674 compatible = "st,stm32-pwm";
676 #pwm-cells = <3>;
679 counter {
680 compatible = "st,stm32-counter";
686 compatible = "st,stm32-timers";
691 interrupt-names = "global";
696 compatible = "st,stm32-pwm";
698 #pwm-cells = <3>;
701 counter {
702 compatible = "st,stm32-counter";
708 compatible = "st,stm32-otgfs";
711 interrupt-names = "otgfs";
712 num-bidir-endpoints = <6>;
713 ram-size = <1280>;
714 maximum-speed = "full-speed";
722 compatible = "st,stm32-otghs";
725 interrupt-names = "otghs", "ep1_out", "ep1_in";
726 num-bidir-endpoints = <9>;
727 ram-size = <4096>;
728 maximum-speed = "full-speed";
736 compatible = "st,stm32-rtc";
741 alarms-count = <2>;
742 alrm-exti-line = <17>;
746 compatible = "st,stm32-bbram";
747 st,backup-regs = <32>;
753 compatible = "st,stm32f4-adc", "st,stm32-adc";
758 #io-channel-cells = <1>;
763 sampling-times = <3 15 28 56 84 112 144 480>;
764 st,adc-clock-source = "SYNC";
765 st,adc-sequencer = "FULLY_CONFIGURABLE";
766 st,adc-oversampler = "OVERSAMPLER_NONE";
770 compatible = "st,stm32f4-adc", "st,stm32-adc";
775 #io-channel-cells = <1>;
780 sampling-times = <3 15 28 56 84 112 144 480>;
781 st,adc-clock-source = "SYNC";
782 st,adc-sequencer = "FULLY_CONFIGURABLE";
783 st,adc-oversampler = "OVERSAMPLER_NONE";
787 compatible = "st,stm32f4-adc", "st,stm32-adc";
792 #io-channel-cells = <1>;
797 sampling-times = <3 15 28 56 84 112 144 480>;
798 st,adc-clock-source = "SYNC";
799 st,adc-sequencer = "FULLY_CONFIGURABLE";
800 st,adc-oversampler = "OVERSAMPLER_NONE";
804 compatible = "st,stm32-dac";
808 #io-channel-cells = <1>;
812 compatible = "st,stm32-dma-v1";
813 #dma-cells = <4>;
821 compatible = "st,stm32-dma-v1";
822 #dma-cells = <4>;
831 compatible = "st,stm32-rng";
840 compatible = "st,stm32-sdmmc";
850 compatible = "zephyr,memory-region", "st,stm32-backup-sram";
853 zephyr,memory-region = "BACKUP_SRAM";
858 compatible = "st,stm32-qspi";
859 #address-cells = <0x1>;
860 #size-cells = <0x0>;
869 compatible = "st,stm32-temp-cal";
870 ts-cal1-addr = <0x1FF0F44C>;
871 ts-cal2-addr = <0x1FF0F44E>;
872 ts-cal1-temp = <30>;
873 ts-cal2-temp = <110>;
874 ts-cal-vrefanalog = <3300>;
875 io-channels = <&adc1 18>;
880 compatible = "st,stm32-vref";
881 vrefint-cal-addr = <0x1FF0F44A>;
882 vrefint-cal-mv = <3300>;
883 io-channels = <&adc1 17>;
888 compatible = "st,stm32-vbat";
890 io-channels = <&adc1 18>;
895 compatible = "usb-nop-xceiv";
896 #phy-cells = <0>;
900 compatible = "usb-nop-xceiv";
901 #phy-cells = <0>;
905 compatible = "st,stm32-smbus";
906 #address-cells = <1>;
907 #size-cells = <0>;
913 compatible = "st,stm32-smbus";
914 #address-cells = <1>;
915 #size-cells = <0>;
921 compatible = "st,stm32-smbus";
922 #address-cells = <1>;
923 #size-cells = <0>;
930 arm,num-irq-priority-bits = <4>;