1/*
2 * Copyright (c) 2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <adi/max32/max32xxx.dtsi>
9#include <zephyr/dt-bindings/dma/max32672_dma.h>
10
11&sram0 {
12	reg = <0x20000000 DT_SIZE_K(16)>;
13};
14
15&clk_inro {
16	clock-frequency = <DT_FREQ_K(80)>;
17};
18
19&i2c2 {
20	clocks = <&gcr ADI_MAX32_CLOCK_BUS1 21>;
21};
22
23/delete-node/ &clk_iso;
24
25&adc {
26	compatible = "adi,max32-adc-sar", "adi,max32-adc";
27	clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
28	clock-divider = <16>;
29	channel-count = <16>;
30	track-count = <4>;
31	idle-count = <0>;
32	vref-mv = <1250>;
33	resolution = <12>;
34};
35
36/* MAX32672 extra peripherals. */
37/ {
38	soc {
39		sram1: memory@20004000 {
40			compatible = "mmio-sram";
41			reg = <0x20004000 DT_SIZE_K(16)>;
42		};
43
44		sram2: memory@20008000 {
45			compatible = "mmio-sram";
46			reg = <0x20008000 DT_SIZE_K(64)>;
47		};
48
49		sram3: memory@20018000 {
50			compatible = "mmio-sram";
51			reg = <0x20018000 DT_SIZE_K(64)>;
52		};
53
54		sram4: memory@20028000 {
55			compatible = "mmio-sram";
56			reg = <0x20028000 DT_SIZE_K(4)>;
57		};
58
59		sram5: memory@20029000 {
60			compatible = "mmio-sram";
61			reg = <0x20029000 DT_SIZE_K(4)>;
62		};
63
64		sram6: memory@2002a000 {
65			compatible = "mmio-sram";
66			reg = <0x2002a000 DT_SIZE_K(16)>;
67		};
68
69		sram7: memory@2002e000 {
70			compatible = "mmio-sram";
71			reg = <0x2002e000 DT_SIZE_K(16)>;
72		};
73
74		flc1: flash_controller@40029400 {
75			compatible = "adi,max32-flash-controller";
76			reg = <0x40029400 0x400>;
77
78			#address-cells = <1>;
79			#size-cells = <1>;
80			status = "okay";
81
82			flash1: flash@10080000 {
83				compatible = "soc-nv-flash";
84				reg = <0x10080000 DT_SIZE_K(512)>;
85				write-block-size = <16>;
86				erase-block-size = <8192>;
87			};
88		};
89
90		uart3: serial@40145000 {
91			compatible = "adi,max32-uart";
92			reg = <0x40145000 0x1000>;
93			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 2>;
94			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
95			interrupts = <88 0>;
96			status = "disabled";
97		};
98
99		dma0: dma@40028000 {
100			compatible = "adi,max32-dma";
101			reg = <0x40028000 0x1000>;
102			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
103			interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>,
104						 <72 0>, <73 0>, <74 0>, <75 0>;
105			dma-channels = <12>;
106			status = "disabled";
107			#dma-cells = <2>;
108		};
109
110		wdt1: watchdog@40003400  {
111			compatible = "adi,max32-watchdog";
112			reg = <0x40003400 0x400>;
113			interrupts = <57 0>;
114			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 5>;
115			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
116			status = "disabled";
117		};
118
119		spi0: spi@40046000 {
120			compatible = "adi,max32-spi";
121			reg = <0x40046000 0x1000>;
122			#address-cells = <1>;
123			#size-cells = <0>;
124			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
125			interrupts = <16 0>;
126			status = "disabled";
127		};
128
129		spi1: spi@40047000 {
130			compatible = "adi,max32-spi";
131			reg = <0x40047000 0x1000>;
132			#address-cells = <1>;
133			#size-cells = <0>;
134			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
135			interrupts = <17 0>;
136			status = "disabled";
137		};
138
139		spi2: spi@40048000 {
140			compatible = "adi,max32-spi";
141			reg = <0x40048000 0x1000>;
142			#address-cells = <1>;
143			#size-cells = <0>;
144			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 8>;
145			interrupts = <18 0>;
146			status = "disabled";
147		};
148
149		lptimer0: timer@40114000 {
150			compatible = "adi,max32-timer";
151			reg = <0x40114000 0x1000>;
152			interrupts = <9 0>;
153			status = "disabled";
154			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
155			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
156			prescaler = <1>;
157			counter {
158				compatible = "adi,max32-counter";
159				status = "disabled";
160			};
161		};
162
163		lptimer1: timer@40115000 {
164			compatible = "adi,max32-timer";
165			reg = <0x40115000 0x1000>;
166			interrupts = <10 0>;
167			status = "disabled";
168			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 1>;
169			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
170			prescaler = <1>;
171			counter {
172				compatible = "adi,max32-counter";
173				status = "disabled";
174			};
175		};
176	};
177};
178