Searched full:sdclk (Results 1 – 20 of 20) sorted by relevance
108 #define RCAR_MMC_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */109 #define RCAR_MMC_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */110 #define RCAR_MMC_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */111 #define RCAR_MMC_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */112 #define RCAR_MMC_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */113 #define RCAR_MMC_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */114 #define RCAR_MMC_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */115 #define RCAR_MMC_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */116 #define RCAR_MMC_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */117 #define RCAR_MMC_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */[all …]
119 * sdclk 10000,444 * Host Controller SDCLK start point adjustment in sdhc_cdns_init_hrs_io()
235 /* HRS10 - Host Controller SDCLK start point adjustment */
324 /* note: be careful soft reset stops SDCLK */ in rcar_mmc_reset()2054 * timeout counter: SDCLK * 2^27 in rcar_mmc_init_controller_regs()
23 sdclk:29 SDCLK enable or disable
94 psels = <RA_PSEL(RA_PSEL_SDHI, 3, 8)>; /* SDCLK */
137 psels = <RA_PSEL(RA_PSEL_SDHI, 3, 8)>; /* SDCLK */
134 - SDCLK: SDRAM clock period. If two SDRAM devices are used both should
142 sdclk = <0>;
186 sdclk = <1>;
240 sdclk = <1>;
339 sdclk = <0>;
390 sdclk = <0>;
260 psels = <RA_PSEL(RA_PSEL_SDHI, 4, 0)>; /* SDCLK */
181 sdclk = <1>;
178 sdclk = <1>;
211 sdclk = <1>;
147 - SDCLK/SDNWE/SDCKE0/SDNE0 : PG8/PH5/PC3/PH3
164 - SDCLK/SDNWE/SDCKE1/SDNE1 : PG8/PH5/PH7/PH6
152 - SDCLK/SDNWE/SDCKE0/SDNE0 : PG8/PH5/PC3/PH3
