1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	sci0_default: sci0_default {
8		group1 {
9			/* tx */
10			psels = <RA_PSEL(RA_PSEL_SCI_0, 6, 9)>;
11			drive-strength = "medium";
12		};
13		group2 {
14			/* rx */
15			psels = <RA_PSEL(RA_PSEL_SCI_0, 6, 10)>;
16		};
17	};
18
19	sci2_default: sci2_default {
20		group1 {
21			/* tx */
22			psels = <RA_PSEL(RA_PSEL_SCI_2, 10, 3)>;
23			drive-strength = "medium";
24		};
25		group2 {
26			/* rx */
27			psels = <RA_PSEL(RA_PSEL_SCI_2, 10, 2)>;
28		};
29	};
30
31	sci3_default: sci3_default {
32		group1 {
33			/* tx */
34			psels = <RA_PSEL(RA_PSEL_SCI_3, 3, 10)>;
35			drive-strength = "medium";
36		};
37		group2 {
38			/* rx */
39			psels = <RA_PSEL(RA_PSEL_SCI_3, 3, 9)>;
40		};
41	};
42
43	sci9_default: sci9_default {
44		group1 {
45			/* tx */
46			psels = <RA_PSEL(RA_PSEL_SCI_9, 10, 14)>;
47			drive-strength = "medium";
48		};
49		group2 {
50			/* rx */
51			psels = <RA_PSEL(RA_PSEL_SCI_9, 10, 15)>;
52		};
53	};
54
55	iic1_default: iic1_default {
56		group1 {
57			/* SCL1 SDA1*/
58			psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>,<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
59			drive-strength = "medium";
60		};
61	};
62
63	adc0_default: adc0_default {
64		group1 {
65			/* input */
66			psels = <RA_PSEL(RA_PSEL_ADC, 0, 4)>;
67			renesas,analog-enable;
68		};
69	};
70
71	spi1_default: spi1_default {
72		group1 {
73			/* MISO MOSI RSPCK SSL*/
74			psels = <RA_PSEL(RA_PSEL_SPI, 4, 10)>,
75			<RA_PSEL(RA_PSEL_SPI, 4, 11)>,
76			<RA_PSEL(RA_PSEL_SPI, 4, 12)>,
77			<RA_PSEL(RA_PSEL_SPI, 4, 13)>;
78		};
79	};
80
81	pwm7_default: pwm7_default {
82		group1 {
83			/* GTIOC7A */
84			psels = <RA_PSEL(RA_PSEL_GPT1, 6, 3)>;
85		};
86		group2 {
87			/* GTIOC7B */
88			psels = <RA_PSEL(RA_PSEL_GPT1, 6, 2)>;
89		};
90	};
91
92	canfd0_default: canfd0_default {
93		group1 {
94			/* CRX0 CTX0 */
95			psels = <RA_PSEL(RA_PSEL_CANFD, 3, 11)>,
96			<RA_PSEL(RA_PSEL_CANFD, 3, 12)>;
97			drive-strength = "high";
98		};
99	};
100
101	ether_default: ether_default {
102		group1 {
103			psels = <RA_PSEL(RA_PSEL_ETH_RMII, 4, 1)>, /* ET0_MDC */
104					<RA_PSEL(RA_PSEL_ETH_RMII, 4, 2)>, /* ET0_MDIO */
105					<RA_PSEL(RA_PSEL_ETH_RMII, 4, 3)>, /* ET0_LINKSTA */
106					<RA_PSEL(RA_PSEL_ETH_RMII, 4, 5)>, /* RMII0_TXD_EN_B */
107					<RA_PSEL(RA_PSEL_ETH_RMII, 4, 6)>, /* RMII0_TXD1_BR */
108					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 0)>, /* RMII0_TXD0_B */
109					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 1)>, /* REF50CK0_B */
110					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 2)>, /* RMII0_RXD0_B */
111					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 3)>, /* RMII0_RXD1_B */
112					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 4)>, /* RMII0_RX_ER_B */
113					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 5)>; /* RMII0_CRS_DV_B */
114			drive-strength = "high";
115		};
116	};
117
118	usbhs_default: usbhs_default {
119		group1 {
120			psels = <RA_PSEL(RA_PSEL_USBHS, 11, 1)>; /* VBUS */
121			drive-strength = "high";
122		};
123	};
124
125	sdhc0_default: sdhc0_default {
126		group1 {
127			psels = <RA_PSEL(RA_PSEL_SDHI, 3, 6)>, /* SDCD */
128			<RA_PSEL(RA_PSEL_SDHI, 3, 7)>, /* SDCMD */
129			<RA_PSEL(RA_PSEL_SDHI, 3, 4)>, /* SDDATA0 */
130			<RA_PSEL(RA_PSEL_SDHI, 3, 3)>, /* SDDATA1 */
131			<RA_PSEL(RA_PSEL_SDHI, 3, 2)>, /* SDDATA2 */
132			<RA_PSEL(RA_PSEL_SDHI, 3, 1)>, /* SDDATA3 */
133			<RA_PSEL(RA_PSEL_SDHI, 3, 5)>; /* SDWP */
134			drive-strength = "high";
135		};
136		group2 {
137			psels = <RA_PSEL(RA_PSEL_SDHI, 3, 8)>; /* SDCLK */
138			drive-strength = "highspeed-high";
139		};
140	};
141};
142