1 /*
2 * Copyright (c) 2023 EPAM Systems
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT renesas_rcar_mmc
8
9 #include <zephyr/devicetree.h>
10 #include <zephyr/drivers/disk.h>
11 #include <zephyr/drivers/sdhc.h>
12 #include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
13 #include <zephyr/drivers/pinctrl.h>
14 #include <zephyr/logging/log.h>
15 #include <zephyr/cache.h>
16 #include <zephyr/drivers/regulator.h>
17
18 #include "rcar_mmc_registers.h"
19
20 #define PINCTRL_STATE_UHS PINCTRL_STATE_PRIV_START
21
22 /**
23 * @note we don't need any locks here, because SDHC subsystem cares about it
24 */
25
26 LOG_MODULE_REGISTER(rcar_mmc, CONFIG_LOG_DEFAULT_LEVEL);
27
28 #define MMC_POLL_FLAGS_TIMEOUT_US 100000
29 #define MMC_POLL_FLAGS_ONE_CYCLE_TIMEOUT_US 1
30 #define MMC_BUS_CLOCK_FREQ 800000000
31
32 #ifdef CONFIG_RCAR_MMC_DMA_SUPPORT
33 #define ALIGN_BUF_DMA __aligned(CONFIG_SDHC_BUFFER_ALIGNMENT)
34 #else
35 #define ALIGN_BUF_DMA
36 #endif
37
38 /**
39 * @brief Renesas MMC host controller driver data
40 *
41 */
42 struct mmc_rcar_data {
43 DEVICE_MMIO_RAM; /* Must be first */
44 struct sdhc_io host_io;
45 struct sdhc_host_props props;
46 #ifdef CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT
47 struct k_sem irq_xref_fin;
48 #endif
49
50 uint8_t ver;
51 /* in bytes, possible values are 2, 4 or 8 */
52 uint8_t width_access_sd_buf0;
53 uint8_t ddr_mode;
54 uint8_t restore_cfg_after_reset;
55 uint8_t is_last_cmd_app_cmd; /* ACMD55 */
56
57 #ifdef CONFIG_RCAR_MMC_SCC_SUPPORT
58 uint8_t manual_retuning;
59 uint8_t tuning_buf[128] ALIGN_BUF_DMA;
60 #endif /* CONFIG_RCAR_MMC_SCC_SUPPORT */
61 uint8_t can_retune;
62 };
63
64 /**
65 * @brief Renesas MMC host controller driver configuration
66 */
67 struct mmc_rcar_cfg {
68 DEVICE_MMIO_ROM; /* Must be first */
69 struct rcar_cpg_clk cpg_clk;
70 struct rcar_cpg_clk bus_clk;
71 const struct device *cpg_dev;
72 const struct pinctrl_dev_config *pcfg;
73 const struct device *regulator_vqmmc;
74 const struct device *regulator_vmmc;
75
76 uint32_t max_frequency;
77
78 #ifdef CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT
79 void (*irq_config_func)(const struct device *dev);
80 #endif
81
82 uint8_t non_removable;
83 uint8_t uhs_support;
84 uint8_t mmc_hs200_1_8v;
85 uint8_t mmc_hs400_1_8v;
86 uint8_t bus_width;
87 uint8_t mmc_sdr104_support;
88 };
89
90 #ifdef CONFIG_RCAR_MMC_SCC_SUPPORT
91 static int rcar_mmc_execute_tuning(const struct device *dev);
92 static int rcar_mmc_retune_if_needed(const struct device *dev, bool request_retune);
93 #endif
94 static int rcar_mmc_disable_scc(const struct device *dev);
95
rcar_mmc_read_reg32(const struct device * dev,uint32_t reg)96 static uint32_t rcar_mmc_read_reg32(const struct device *dev, uint32_t reg)
97 {
98 return sys_read32(DEVICE_MMIO_GET(dev) + reg);
99 }
100
rcar_mmc_write_reg32(const struct device * dev,uint32_t reg,uint32_t val)101 static void rcar_mmc_write_reg32(const struct device *dev, uint32_t reg, uint32_t val)
102 {
103 sys_write32(val, DEVICE_MMIO_GET(dev) + reg);
104 }
105
106 /* cleanup SD card interrupt flag register and mask their interrupts */
rcar_mmc_reset_and_mask_irqs(const struct device * dev)107 static inline void rcar_mmc_reset_and_mask_irqs(const struct device *dev)
108 {
109 struct mmc_rcar_data *data = dev->data;
110
111 rcar_mmc_write_reg32(dev, RCAR_MMC_INFO1, 0);
112 rcar_mmc_write_reg32(dev, RCAR_MMC_INFO1_MASK, ~0);
113
114 rcar_mmc_write_reg32(dev, RCAR_MMC_INFO2, RCAR_MMC_INFO2_CLEAR);
115 rcar_mmc_write_reg32(dev, RCAR_MMC_INFO2_MASK, ~0);
116
117 #ifdef CONFIG_RCAR_MMC_DMA_SUPPORT
118 /* default value of Seq suspend should be 0 */
119 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO1_MASK, 0xfffffeff);
120 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO1, 0x0);
121 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO2_MASK, 0xffffffff);
122 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO2, 0x0);
123 #ifdef CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT
124 k_sem_reset(&data->irq_xref_fin);
125 #endif
126 #endif /* CONFIG_RCAR_MMC_DMA_SUPPORT */
127 }
128
129 /**
130 * @brief check if MMC is busy
131 *
132 * This check should generally be implemented as checking the controller
133 * state. No MMC commands need to be sent.
134 *
135 * @param dev MMC device
136 * @retval 0 card is not busy
137 * @retval 1 card is busy
138 * @retval -EINVAL: the dev pointer is NULL
139 */
rcar_mmc_card_busy(const struct device * dev)140 static int rcar_mmc_card_busy(const struct device *dev)
141 {
142 uint32_t reg;
143
144 if (!dev) {
145 return -EINVAL;
146 }
147
148 reg = rcar_mmc_read_reg32(dev, RCAR_MMC_INFO2);
149 return (reg & RCAR_MMC_INFO2_DAT0) ? 0 : 1;
150 }
151
152 /**
153 * @brief Check error flags inside INFO2 MMC register
154 *
155 * @note in/out parameters should be checked by a caller function
156 *
157 * @param dev MMC device
158 *
159 * @retval 0 INFO2 register hasn't errors
160 * @retval -ETIMEDOUT: timed out while tx/rx
161 * @retval -EIO: I/O error
162 * @retval -EILSEQ: communication out of sync
163 */
rcar_mmc_check_errors(const struct device * dev)164 static int rcar_mmc_check_errors(const struct device *dev)
165 {
166 uint32_t info2 = rcar_mmc_read_reg32(dev, RCAR_MMC_INFO2);
167
168 if (info2 & (RCAR_MMC_INFO2_ERR_TO | RCAR_MMC_INFO2_ERR_RTO)) {
169 LOG_DBG("timeout error 0x%08x", info2);
170 return -ETIMEDOUT;
171 }
172
173 if (info2 & (RCAR_MMC_INFO2_ERR_END | RCAR_MMC_INFO2_ERR_CRC | RCAR_MMC_INFO2_ERR_IDX)) {
174 LOG_DBG("communication out of sync 0x%08x", info2);
175 return -EILSEQ;
176 }
177
178 if (info2 & (RCAR_MMC_INFO2_ERR_ILA | RCAR_MMC_INFO2_ERR_ILR | RCAR_MMC_INFO2_ERR_ILW)) {
179 LOG_DBG("illegal access 0x%08x", info2);
180 return -EIO;
181 }
182
183 return 0;
184 }
185
186 /**
187 * @brief Poll flag(s) in MMC register and check errors
188 *
189 * @note in/out parameters should be checked by a caller function
190 *
191 * @param dev MMC device
192 * @param reg register offset relative to the base address
193 * @param flag polling flag(s)
194 * @param state state of flag(s) when we should stop polling
195 * @param check_errors call @ref rcar_mmc_check_errors function or not
196 * @param check_dma_errors check if there are DMA errors inside info2
197 * @param timeout_us timeout in microseconds how long we should poll flag(s)
198 *
199 * @retval 0 poll of flag(s) was successful
200 * @retval -ETIMEDOUT: timed out while tx/rx
201 * @retval -EIO: I/O error
202 * @retval -EILSEQ: communication out of sync
203 */
rcar_mmc_poll_reg_flags_check_err(const struct device * dev,unsigned int reg,uint32_t flag,uint32_t state,bool check_errors,bool check_dma_errors,int64_t timeout_us)204 static int rcar_mmc_poll_reg_flags_check_err(const struct device *dev, unsigned int reg,
205 uint32_t flag, uint32_t state, bool check_errors,
206 bool check_dma_errors, int64_t timeout_us)
207 {
208 int ret;
209
210 while ((rcar_mmc_read_reg32(dev, reg) & flag) != state) {
211 if (timeout_us < 0) {
212 LOG_DBG("timeout error during polling flag(s) 0x%08x in reg 0x%08x", flag,
213 reg);
214 return -ETIMEDOUT;
215 }
216
217 if (check_errors) {
218 ret = rcar_mmc_check_errors(dev);
219 if (ret) {
220 return ret;
221 }
222 }
223
224 if (check_dma_errors && rcar_mmc_read_reg32(dev, RCAR_MMC_DMA_INFO2)) {
225 LOG_DBG("%s: an error occurs on the DMAC channel #%u", dev->name,
226 (reg & RCAR_MMC_DMA_INFO2_ERR_RD) ? 1U : 0U);
227 return -EIO;
228 }
229
230 k_usleep(MMC_POLL_FLAGS_ONE_CYCLE_TIMEOUT_US);
231 timeout_us -= MMC_POLL_FLAGS_ONE_CYCLE_TIMEOUT_US;
232 }
233
234 return 0;
235 }
236
237 /* reset DMA MMC controller */
rcar_mmc_reset_dma(const struct device * dev)238 static inline void rcar_mmc_reset_dma(const struct device *dev)
239 {
240 uint32_t reg = RCAR_MMC_DMA_RST_DTRAN0 | RCAR_MMC_DMA_RST_DTRAN1;
241
242 rcar_mmc_write_reg32(dev, RCAR_MMC_EXTMODE, 0);
243 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_RST, ~reg);
244 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_RST, ~0);
245 rcar_mmc_write_reg32(dev, RCAR_MMC_EXTMODE, 1);
246 }
247
248 /**
249 * @brief reset MMC controller state
250 *
251 * Used when the MMC has encountered an error. Resetting the MMC controller
252 * should clear all errors on the MMC, but does not necessarily reset I/O
253 * settings to boot (this can be done with @ref sdhc_set_io)
254 *
255 * @note during reset the clock input is disabled, also this call changes rate
256 *
257 * @param dev MMC controller device
258 * @retval 0 reset succeeded
259 * @retval -ETIMEDOUT: controller reset timed out
260 * @retval -EINVAL: the dev pointer is NULL
261 * @retval -EILSEQ: communication out of sync
262 * @retval -ENOTSUP: controller does not support I/O
263 *
264 * @details List of affected registers and their bits during the soft reset trigger:
265 * * RCAR_MMC_STOP all bits reset to default (0x0);
266 * * RCAR_MMC_INFO1 affected bits:
267 * * RCAR_MMC_INFO1_CMP default state 0;
268 * * RCAR_MMC_INFO1_RSP default state 0;
269 * * HPIRES Response Reception Completion (16), default state 0;
270 * * RCAR_MMC_INFO2 all bits reset 0, except the next:
271 * * RCAR_MMC_INFO2_DAT0 state unknown after reset;
272 * * RCAR_MMC_INFO2_SCLKDIVEN default state 1;
273 * * RCAR_MMC_CLKCTL affected bit(s):
274 * * RCAR_MMC_CLKCTL_SCLKEN default state 0;
275 * * RCAR_MMC_OPTION affected bits:
276 * * WIDTH (15) and WIDTH8 (13) set to 0, which equal to 4-bits bus;
277 * * Timeout Mode Select (EXTOP - 9) is set to 0;
278 * * Timeout Mask (TOUTMASK - 8) is set to 0;
279 * * Timeout Counter (TOP27-TOP24 bits 7-4) is equal to 0b1110;
280 * * Card Detect Time Counter (CTOP24-CTOP21 bits 3-0) is equal to 0b1110;
281 * * RCAR_MMC_ERR_STS1 all bits after reset 0, except the next:
282 * * E13 default state 1 (E12-E14 it is CRC status 0b010);
283 * * RCAR_MMC_ERR_STS2 all bits after reset 0;
284 * * IO_INFO1 all bits after reset 0;
285 * * RCAR_MMC_IF_MODE all bits after reset 0.
286 */
rcar_mmc_reset(const struct device * dev)287 static int rcar_mmc_reset(const struct device *dev)
288 {
289 int ret = 0;
290 uint32_t reg;
291 struct mmc_rcar_data *data;
292 uint8_t can_retune;
293
294 if (!dev) {
295 return -EINVAL;
296 }
297
298 data = dev->data;
299
300 /*
301 * soft reset of the host
302 */
303 reg = rcar_mmc_read_reg32(dev, RCAR_MMC_SOFT_RST);
304 reg &= ~RCAR_MMC_SOFT_RST_RSTX;
305 rcar_mmc_write_reg32(dev, RCAR_MMC_SOFT_RST, reg);
306 reg |= RCAR_MMC_SOFT_RST_RSTX;
307 rcar_mmc_write_reg32(dev, RCAR_MMC_SOFT_RST, reg);
308
309 rcar_mmc_reset_and_mask_irqs(dev);
310
311 /*
312 * note: DMA reset can be triggered only in case of error in
313 * DMA Info2 otherwise the SDIP will not accurately operate
314 */
315 #ifdef CONFIG_RCAR_MMC_DMA_SUPPORT
316 rcar_mmc_reset_dma(dev);
317 #endif
318
319 can_retune = data->can_retune;
320 if (can_retune) {
321 rcar_mmc_disable_scc(dev);
322 }
323
324 /* note: be careful soft reset stops SDCLK */
325 if (data->restore_cfg_after_reset) {
326 struct sdhc_io ios;
327
328 memcpy(&ios, &data->host_io, sizeof(ios));
329 memset(&data->host_io, 0, sizeof(ios));
330
331 data->host_io.power_mode = ios.power_mode;
332
333 ret = sdhc_set_io(dev, &ios);
334
335 rcar_mmc_write_reg32(dev, RCAR_MMC_STOP, RCAR_MMC_STOP_SEC);
336
337 #ifdef CONFIG_RCAR_MMC_SCC_SUPPORT
338 /* tune if this reset isn't invoked during tuning */
339 if (can_retune && (ios.timing == SDHC_TIMING_SDR50 ||
340 ios.timing == SDHC_TIMING_SDR104 ||
341 ios.timing == SDHC_TIMING_HS200)) {
342 ret = rcar_mmc_execute_tuning(dev);
343 }
344 #endif
345
346 return ret;
347 }
348
349 data->ddr_mode = 0;
350 data->host_io.bus_width = SDHC_BUS_WIDTH4BIT;
351 data->host_io.timing = SDHC_TIMING_LEGACY;
352 data->is_last_cmd_app_cmd = 0;
353
354 return 0;
355 }
356
357 /**
358 * @brief SD Clock (SD_CLK) Output Control Enable
359 *
360 * @note in/out parameters should be checked by a caller function.
361 *
362 * @param dev MMC device
363 * @param enable
364 * false: SD_CLK output is disabled. The SD_CLK signal is fixed 0.
365 * true: SD_CLK output is enabled.
366 *
367 * @retval 0 I/O was configured correctly
368 * @retval -ETIMEDOUT: card busy flag is set during long time
369 */
rcar_mmc_enable_clock(const struct device * dev,bool enable)370 static int rcar_mmc_enable_clock(const struct device *dev, bool enable)
371 {
372 int ret;
373 uint32_t mmc_clk_ctl = rcar_mmc_read_reg32(dev, RCAR_MMC_CLKCTL);
374
375 if (enable == true) {
376 mmc_clk_ctl &= ~RCAR_MMC_CLKCTL_OFFEN;
377 mmc_clk_ctl |= RCAR_MMC_CLKCTL_SCLKEN;
378 } else {
379 mmc_clk_ctl |= RCAR_MMC_CLKCTL_OFFEN;
380 mmc_clk_ctl &= ~RCAR_MMC_CLKCTL_SCLKEN;
381 }
382
383 /*
384 * Do not change the values of these bits
385 * when the CBSY bit in SD_INFO2 is 1
386 */
387 ret = rcar_mmc_poll_reg_flags_check_err(dev, RCAR_MMC_INFO2, RCAR_MMC_INFO2_CBSY, 0, false,
388 false, MMC_POLL_FLAGS_TIMEOUT_US);
389 if (ret) {
390 return -ETIMEDOUT;
391 }
392 rcar_mmc_write_reg32(dev, RCAR_MMC_CLKCTL, mmc_clk_ctl);
393
394 /* SD spec recommends at least 1 ms of delay */
395 k_msleep(1);
396
397 return 0;
398 }
399
400 /**
401 * @brief Convert SDHC response to Renesas MMC response
402 *
403 * Function performs a conversion from SDHC response to Renesas MMC
404 * CMD register response.
405 *
406 * @note in/out parameters should be checked by a caller function.
407 *
408 * @param response_type SDHC response type without SPI flags
409 *
410 * @retval positiv number (partial configuration of CMD register) on
411 * success, negative errno code otherwise
412 */
rcar_mmc_convert_sd_to_mmc_resp(uint32_t response_type)413 static int32_t rcar_mmc_convert_sd_to_mmc_resp(uint32_t response_type)
414 {
415 uint32_t mmc_resp = 0U;
416
417 switch (response_type) {
418 case SD_RSP_TYPE_NONE:
419 mmc_resp = RCAR_MMC_CMD_RSP_NONE;
420 break;
421 case SD_RSP_TYPE_R1:
422 case SD_RSP_TYPE_R5:
423 case SD_RSP_TYPE_R6:
424 case SD_RSP_TYPE_R7:
425 mmc_resp = RCAR_MMC_CMD_RSP_R1;
426 break;
427 case SD_RSP_TYPE_R1b:
428 case SD_RSP_TYPE_R5b:
429 mmc_resp = RCAR_MMC_CMD_RSP_R1B;
430 break;
431 case SD_RSP_TYPE_R2:
432 mmc_resp = RCAR_MMC_CMD_RSP_R2;
433 break;
434 case SD_RSP_TYPE_R3:
435 case SD_RSP_TYPE_R4:
436 mmc_resp = RCAR_MMC_CMD_RSP_R3;
437 break;
438 default:
439 LOG_ERR("unknown response type 0x%08x", response_type);
440 return -EINVAL;
441 }
442
443 __ASSERT((int32_t)mmc_resp >= 0, "%s: converted response shouldn't be negative", __func__);
444
445 return mmc_resp;
446 }
447
448 /**
449 * @brief Convert response from Renesas MMC to SDHC
450 *
451 * Function writes a response to response array of @ref sdhc_command structure
452 *
453 * @note in/out parameters should be checked by a caller function.
454 *
455 * @param dev MMC device
456 * @param cmd MMC command
457 * @param response_type SDHC response type without SPI flags
458 *
459 * @retval none
460 */
rcar_mmc_extract_resp(const struct device * dev,struct sdhc_command * cmd,uint32_t response_type)461 static void rcar_mmc_extract_resp(const struct device *dev, struct sdhc_command *cmd,
462 uint32_t response_type)
463 {
464 if (response_type == SD_RSP_TYPE_R2) {
465 uint32_t rsp_127_104 = rcar_mmc_read_reg32(dev, RCAR_MMC_RSP76);
466 uint32_t rsp_103_72 = rcar_mmc_read_reg32(dev, RCAR_MMC_RSP54);
467 uint32_t rsp_71_40 = rcar_mmc_read_reg32(dev, RCAR_MMC_RSP32);
468 uint32_t rsp_39_8 = rcar_mmc_read_reg32(dev, RCAR_MMC_RSP10);
469
470 cmd->response[0] = (rsp_39_8 & 0xffffff) << 8;
471 cmd->response[1] =
472 ((rsp_71_40 & 0x00ffffff) << 8) | ((rsp_39_8 & 0xff000000) >> 24);
473 cmd->response[2] =
474 ((rsp_103_72 & 0x00ffffff) << 8) | ((rsp_71_40 & 0xff000000) >> 24);
475 cmd->response[3] =
476 ((rsp_127_104 & 0x00ffffff) << 8) | ((rsp_103_72 & 0xff000000) >> 24);
477
478 LOG_DBG("Response 2\n\t[0]: 0x%08x\n\t[1]: 0x%08x"
479 "\n\t[2]: 0x%08x\n\t[3]: 0x%08x",
480 cmd->response[0], cmd->response[1], cmd->response[2], cmd->response[3]);
481 } else {
482 cmd->response[0] = rcar_mmc_read_reg32(dev, RCAR_MMC_RSP10);
483 LOG_DBG("Response %u\n\t[0]: 0x%08x", response_type, cmd->response[0]);
484 }
485 }
486
487 /* configure CMD register for tx/rx data */
rcar_mmc_gen_data_cmd(struct sdhc_command * cmd,struct sdhc_data * data)488 static uint32_t rcar_mmc_gen_data_cmd(struct sdhc_command *cmd, struct sdhc_data *data)
489 {
490 uint32_t cmd_reg = RCAR_MMC_CMD_DATA;
491
492 switch (cmd->opcode) {
493 case MMC_SEND_EXT_CSD:
494 case SD_READ_SINGLE_BLOCK:
495 case MMC_SEND_TUNING_BLOCK:
496 case SD_SEND_TUNING_BLOCK:
497 case SD_SWITCH:
498 case SD_APP_SEND_NUM_WRITTEN_BLK:
499 case SD_APP_SEND_SCR:
500 cmd_reg |= RCAR_MMC_CMD_RD;
501 break;
502 case SD_READ_MULTIPLE_BLOCK:
503 cmd_reg |= RCAR_MMC_CMD_RD;
504 cmd_reg |= RCAR_MMC_CMD_MULTI;
505 break;
506 case SD_WRITE_MULTIPLE_BLOCK:
507 cmd_reg |= RCAR_MMC_CMD_MULTI;
508 break;
509 case SD_WRITE_SINGLE_BLOCK:
510 /* fall through */
511 default:
512 break;
513 }
514
515 if (data->blocks > 1) {
516 cmd_reg |= RCAR_MMC_CMD_MULTI;
517 }
518
519 return cmd_reg;
520 }
521
522 /**
523 * @brief Transmit/Receive data to/from MMC using DMA
524 *
525 * Sends/Receives data to/from the MMC controller.
526 *
527 * @note in/out parameters should be checked by a caller function.
528 *
529 * @param dev MMC device
530 * @param data MMC data buffer for tx/rx
531 * @param is_read it is read or write operation
532 *
533 * @retval 0 tx/rx was successful
534 * @retval -ENOTSUP: cache flush/invalidate aren't supported
535 * @retval -ETIMEDOUT: timed out while tx/rx
536 * @retval -EIO: I/O error
537 * @retval -EILSEQ: communication out of sync
538 */
rcar_mmc_dma_rx_tx_data(const struct device * dev,struct sdhc_data * data,bool is_read)539 static int rcar_mmc_dma_rx_tx_data(const struct device *dev, struct sdhc_data *data, bool is_read)
540 {
541 uintptr_t dma_addr;
542 uint32_t reg;
543 int ret = 0;
544 uint32_t dma_info1_poll_flag;
545 #ifdef CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT
546 struct mmc_rcar_data *dev_data = dev->data;
547 #endif
548
549 ret = sys_cache_data_flush_range(data->data, data->blocks * data->block_size);
550 if (ret < 0) {
551 LOG_ERR("%s: can't invalidate data cache before write", dev->name);
552 return ret;
553 }
554
555 reg = rcar_mmc_read_reg32(dev, RCAR_MMC_DMA_MODE);
556 if (is_read) {
557 dma_info1_poll_flag = RCAR_MMC_DMA_INFO1_END_RD2;
558 reg |= RCAR_MMC_DMA_MODE_DIR_RD;
559 } else {
560 dma_info1_poll_flag = RCAR_MMC_DMA_INFO1_END_WR;
561 reg &= ~RCAR_MMC_DMA_MODE_DIR_RD;
562 }
563 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_MODE, reg);
564
565 reg = rcar_mmc_read_reg32(dev, RCAR_MMC_EXTMODE);
566 reg |= RCAR_MMC_EXTMODE_DMA_EN;
567 rcar_mmc_write_reg32(dev, RCAR_MMC_EXTMODE, reg);
568
569 dma_addr = k_mem_phys_addr(data->data);
570
571 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_ADDR_L, dma_addr);
572 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_ADDR_H, 0);
573
574 #ifdef CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT
575 rcar_mmc_write_reg32(
576 dev, RCAR_MMC_DMA_INFO2_MASK,
577 (uint32_t)(is_read ? (~RCAR_MMC_DMA_INFO2_ERR_RD) : (~RCAR_MMC_DMA_INFO2_ERR_WR)));
578
579 reg = rcar_mmc_read_reg32(dev, RCAR_MMC_DMA_INFO1_MASK);
580 reg &= ~dma_info1_poll_flag;
581 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO1_MASK, reg);
582 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_CTL, RCAR_MMC_DMA_CTL_START);
583
584 ret = k_sem_take(&dev_data->irq_xref_fin, K_MSEC(data->timeout_ms));
585 if (ret < 0) {
586 LOG_ERR("%s: interrupt signal timeout error %d", dev->name, ret);
587 }
588
589 reg = rcar_mmc_read_reg32(dev, RCAR_MMC_DMA_INFO2);
590 if (reg) {
591 LOG_ERR("%s: an error occurs on the DMAC channel #%u", dev->name,
592 (reg & RCAR_MMC_DMA_INFO2_ERR_RD) ? 1U : 0U);
593 ret = -EIO;
594 }
595 #else
596 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_CTL, RCAR_MMC_DMA_CTL_START);
597 ret = rcar_mmc_poll_reg_flags_check_err(dev, RCAR_MMC_DMA_INFO1, dma_info1_poll_flag,
598 dma_info1_poll_flag, false, true,
599 data->timeout_ms * 1000LL);
600 #endif
601
602 if (is_read) {
603 if (sys_cache_data_invd_range(data->data, data->blocks * data->block_size) < 0) {
604 LOG_ERR("%s: can't invalidate data cache after read", dev->name);
605 }
606 }
607
608 /* in case when we get to here and there wasn't IRQ trigger */
609 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO1_MASK, 0xfffffeff);
610 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO2_MASK, ~0);
611
612 if (ret == -EIO) {
613 rcar_mmc_reset_dma(dev);
614 }
615
616 reg = rcar_mmc_read_reg32(dev, RCAR_MMC_EXTMODE);
617 reg &= ~RCAR_MMC_EXTMODE_DMA_EN;
618 rcar_mmc_write_reg32(dev, RCAR_MMC_EXTMODE, reg);
619
620 return ret;
621 }
622
623 /* read from SD/MMC controller buf0 register */
rcar_mmc_read_buf0(const struct device * dev)624 static inline uint64_t rcar_mmc_read_buf0(const struct device *dev)
625 {
626 uint64_t buf0 = 0ULL;
627 struct mmc_rcar_data *dev_data = dev->data;
628 uint8_t sd_buf0_size = dev_data->width_access_sd_buf0;
629 mm_reg_t buf0_addr = DEVICE_MMIO_GET(dev) + RCAR_MMC_BUF0;
630
631 switch (sd_buf0_size) {
632 case 8:
633 buf0 = sys_read64(buf0_addr);
634 break;
635 case 4:
636 buf0 = sys_read32(buf0_addr);
637 break;
638 case 2:
639 buf0 = sys_read16(buf0_addr);
640 break;
641 default:
642 k_panic();
643 break;
644 }
645
646 return buf0;
647 }
648
649 /* write to SD/MMC controller buf0 register */
rcar_mmc_write_buf0(const struct device * dev,uint64_t val)650 static inline void rcar_mmc_write_buf0(const struct device *dev, uint64_t val)
651 {
652 struct mmc_rcar_data *dev_data = dev->data;
653 uint8_t sd_buf0_size = dev_data->width_access_sd_buf0;
654 mm_reg_t buf0_addr = DEVICE_MMIO_GET(dev) + RCAR_MMC_BUF0;
655
656 switch (sd_buf0_size) {
657 case 8:
658 sys_write64(val, buf0_addr);
659 break;
660 case 4:
661 sys_write32(val, buf0_addr);
662 break;
663 case 2:
664 sys_write16(val, buf0_addr);
665 break;
666 default:
667 k_panic();
668 break;
669 }
670 }
671
672 /**
673 * @brief Transmit/Receive data to/from MMC without DMA
674 *
675 * Sends/Receives data to/from the MMC controller.
676 *
677 * @note in/out parameters should be checked by a caller function.
678 *
679 * @param dev MMC device
680 * @param data MMC data buffer for tx/rx
681 * @param is_read it is read or write operation
682 *
683 * @retval 0 tx/rx was successful
684 * @retval -EINVAL: invalid block size
685 * @retval -ETIMEDOUT: timed out while tx/rx
686 * @retval -EIO: I/O error
687 * @retval -EILSEQ: communication out of sync
688 */
rcar_mmc_sd_buf_rx_tx_data(const struct device * dev,struct sdhc_data * data,bool is_read)689 static int rcar_mmc_sd_buf_rx_tx_data(const struct device *dev, struct sdhc_data *data,
690 bool is_read)
691 {
692 struct mmc_rcar_data *dev_data = dev->data;
693 uint32_t block;
694 int ret = 0;
695 uint32_t info2_poll_flag = is_read ? RCAR_MMC_INFO2_BRE : RCAR_MMC_INFO2_BWE;
696 uint8_t sd_buf0_size = dev_data->width_access_sd_buf0;
697 uint16_t aligned_block_size = ROUND_UP(data->block_size, sd_buf0_size);
698 uint32_t cmd_reg = 0;
699 int64_t remaining_timeout_us = data->timeout_ms * 1000LL;
700
701 /*
702 * note: below code should work for all possible block sizes, but
703 * we need below check, because code isn't tested with smaller
704 * block sizes.
705 */
706 if ((data->block_size % dev_data->width_access_sd_buf0) ||
707 (data->block_size < dev_data->width_access_sd_buf0)) {
708 LOG_ERR("%s: block size (%u) less or not align on SD BUF0 access width (%hhu)",
709 dev->name, data->block_size, dev_data->width_access_sd_buf0);
710 return -EINVAL;
711 }
712
713 /*
714 * JEDEC Standard No. 84-B51
715 * 6.6.24 Dual Data Rate mode operation:
716 * Therefore, all single or multiple block data transfer read or write will operate on
717 * a fixed block size of 512 bytes while the Device remains in dual data rate.
718 *
719 * Physical Layer Specification Version 3.01
720 * 4.12.6 Timing Changes in DDR50 Mode
721 * 4.12.6.2 Protocol Principles
722 * * Read and Write data block length size is always 512 bytes (same as SDHC).
723 */
724 if (dev_data->ddr_mode && data->block_size != 512) {
725 LOG_ERR("%s: block size (%u) isn't equal to 512 in DDR mode", dev->name,
726 data->block_size);
727 return -EINVAL;
728 }
729
730 /*
731 * note: the next restrictions we have according to description of
732 * transfer data length register from R-Car S4 series User's Manual
733 */
734 if (data->block_size > 512 || data->block_size == 0) {
735 LOG_ERR("%s: block size (%u) must not be bigger than 512 bytes and equal to zero",
736 dev->name, data->block_size);
737 return -EINVAL;
738 }
739
740 cmd_reg = rcar_mmc_read_reg32(dev, RCAR_MMC_CMD);
741 if (cmd_reg & RCAR_MMC_CMD_MULTI) {
742 /* CMD12 is automatically issued at multiple block transfer */
743 if (!(cmd_reg & RCAR_MMC_CMD_NOSTOP) && data->block_size != 512) {
744 LOG_ERR("%s: illegal block size (%u) for multi-block xref with CMD12",
745 dev->name, data->block_size);
746 return -EINVAL;
747 }
748
749 switch (data->block_size) {
750 case 32:
751 case 64:
752 case 128:
753 case 256:
754 case 512:
755 break;
756 default:
757 LOG_ERR("%s: illegal block size (%u) for multi-block xref without CMD12",
758 dev->name, data->block_size);
759 return -EINVAL;
760 }
761 }
762
763 if (data->block_size == 1 && dev_data->host_io.bus_width == SDHC_BUS_WIDTH8BIT) {
764 LOG_ERR("%s: block size can't be equal to 1 with 8-bits bus width", dev->name);
765 return -EINVAL;
766 }
767
768 for (block = 0; block < data->blocks; block++) {
769 uint8_t *buf = (uint8_t *)data->data + (block * data->block_size);
770 uint32_t info2_reg;
771 uint16_t w_off; /* word offset in a block */
772 uint64_t start_block_xref_us = k_ticks_to_us_ceil64(k_uptime_ticks());
773
774 /* wait until the buffer is filled with data */
775 ret = rcar_mmc_poll_reg_flags_check_err(dev, RCAR_MMC_INFO2, info2_poll_flag,
776 info2_poll_flag, true, false,
777 remaining_timeout_us);
778 if (ret) {
779 return ret;
780 }
781
782 /* clear write/read buffer ready flag */
783 info2_reg = rcar_mmc_read_reg32(dev, RCAR_MMC_INFO2);
784 info2_reg &= ~info2_poll_flag;
785 rcar_mmc_write_reg32(dev, RCAR_MMC_INFO2, info2_reg);
786
787 for (w_off = 0; w_off < aligned_block_size; w_off += sd_buf0_size) {
788 uint64_t buf0 = 0ULL;
789 uint8_t copy_size = MIN(sd_buf0_size, data->block_size - w_off);
790
791 if (is_read) {
792 buf0 = rcar_mmc_read_buf0(dev);
793 memcpy(buf + w_off, &buf0, copy_size);
794 } else {
795 memcpy(&buf0, buf + w_off, copy_size);
796 rcar_mmc_write_buf0(dev, buf0);
797 }
798 }
799
800 remaining_timeout_us -=
801 k_ticks_to_us_ceil64(k_uptime_ticks()) - start_block_xref_us;
802 if (remaining_timeout_us < 0) {
803 return -ETIMEDOUT;
804 }
805 }
806
807 return ret;
808 }
809
810 /**
811 * @brief Transmit/Receive data to/from MMC
812 *
813 * Sends/Receives data to/from the MMC controller.
814 *
815 * @note in/out parameters should be checked by a caller function.
816 *
817 * @param dev MMC device
818 * @param data MMC data buffer for tx/rx
819 * @param is_read it is read or write operation
820 *
821 * @retval 0 tx/rx was successful
822 * @retval -EINVAL: invalid block size
823 * @retval -ETIMEDOUT: timed out while tx/rx
824 * @retval -EIO: I/O error
825 * @retval -EILSEQ: communication out of sync
826 */
rcar_mmc_rx_tx_data(const struct device * dev,struct sdhc_data * data,bool is_read)827 static int rcar_mmc_rx_tx_data(const struct device *dev, struct sdhc_data *data, bool is_read)
828 {
829 uint32_t info1_reg;
830 int ret = 0;
831
832 #ifdef CONFIG_RCAR_MMC_DMA_SUPPORT
833 if (!(k_mem_phys_addr(data->data) >> 32)) {
834 ret = rcar_mmc_dma_rx_tx_data(dev, data, is_read);
835 } else
836 #endif
837 {
838 ret = rcar_mmc_sd_buf_rx_tx_data(dev, data, is_read);
839 }
840
841 if (ret < 0) {
842 return ret;
843 }
844
845 ret = rcar_mmc_poll_reg_flags_check_err(dev, RCAR_MMC_INFO1, RCAR_MMC_INFO1_CMP,
846 RCAR_MMC_INFO1_CMP, true, false,
847 MMC_POLL_FLAGS_TIMEOUT_US);
848 if (ret) {
849 return ret;
850 }
851
852 /* clear access end flag */
853 info1_reg = rcar_mmc_read_reg32(dev, RCAR_MMC_INFO1);
854 info1_reg &= ~RCAR_MMC_INFO1_CMP;
855 rcar_mmc_write_reg32(dev, RCAR_MMC_INFO1, info1_reg);
856
857 return ret;
858 }
859
860 /**
861 * @brief Send command to MMC
862 *
863 * Sends a command to the MMC controller.
864 *
865 * @param dev MMC device
866 * @param cmd MMC command
867 * @param data MMC data. Leave NULL to send SD command without data.
868 *
869 * @retval 0 command was sent successfully
870 * @retval -ETIMEDOUT: command timed out while sending
871 * @retval -ENOTSUP: host controller does not support command
872 * @retval -EIO: I/O error
873 * @retval -EILSEQ: communication out of sync
874 */
rcar_mmc_request(const struct device * dev,struct sdhc_command * cmd,struct sdhc_data * data)875 static int rcar_mmc_request(const struct device *dev, struct sdhc_command *cmd,
876 struct sdhc_data *data)
877 {
878 int ret = -ENOTSUP;
879 uint32_t reg;
880 uint32_t response_type;
881 bool is_read = true;
882 int attempts;
883 struct mmc_rcar_data *dev_data;
884
885 if (!dev || !cmd) {
886 return -EINVAL;
887 }
888
889 dev_data = dev->data;
890 response_type = cmd->response_type & SDHC_NATIVE_RESPONSE_MASK;
891 attempts = cmd->retries + 1;
892
893 while (ret && attempts-- > 0) {
894 if (ret != -ENOTSUP) {
895 rcar_mmc_reset(dev);
896 #ifdef CONFIG_RCAR_MMC_SCC_SUPPORT
897 rcar_mmc_retune_if_needed(dev, true);
898 #endif
899 }
900
901 ret = rcar_mmc_poll_reg_flags_check_err(dev, RCAR_MMC_INFO2, RCAR_MMC_INFO2_CBSY, 0,
902 false, false, MMC_POLL_FLAGS_TIMEOUT_US);
903 if (ret) {
904 ret = -EBUSY;
905 continue;
906 }
907
908 rcar_mmc_reset_and_mask_irqs(dev);
909
910 rcar_mmc_write_reg32(dev, RCAR_MMC_ARG, cmd->arg);
911
912 reg = cmd->opcode;
913
914 if (data) {
915 rcar_mmc_write_reg32(dev, RCAR_MMC_SIZE, data->block_size);
916 rcar_mmc_write_reg32(dev, RCAR_MMC_SECCNT, data->blocks);
917 reg |= rcar_mmc_gen_data_cmd(cmd, data);
918 is_read = (reg & RCAR_MMC_CMD_RD) ? true : false;
919 }
920
921 /* CMD55 is always sended before ACMD */
922 if (dev_data->is_last_cmd_app_cmd) {
923 reg |= RCAR_MMC_CMD_APP;
924 }
925
926 ret = rcar_mmc_convert_sd_to_mmc_resp(response_type);
927 if (ret < 0) {
928 /* don't need to retry we will always have the same result */
929 return -EINVAL;
930 }
931
932 reg |= ret;
933
934 LOG_DBG("(SD_CMD=%08x, SD_ARG=%08x)", cmd->opcode, cmd->arg);
935 rcar_mmc_write_reg32(dev, RCAR_MMC_CMD, reg);
936
937 /* wait until response end flag is set or errors occur */
938 ret = rcar_mmc_poll_reg_flags_check_err(dev, RCAR_MMC_INFO1, RCAR_MMC_INFO1_RSP,
939 RCAR_MMC_INFO1_RSP, true, false,
940 cmd->timeout_ms * 1000LL);
941 if (ret) {
942 continue;
943 }
944
945 /* clear response end flag */
946 reg = rcar_mmc_read_reg32(dev, RCAR_MMC_INFO1);
947 reg &= ~RCAR_MMC_INFO1_RSP;
948 rcar_mmc_write_reg32(dev, RCAR_MMC_INFO1, reg);
949
950 rcar_mmc_extract_resp(dev, cmd, response_type);
951
952 if (data) {
953 ret = rcar_mmc_rx_tx_data(dev, data, is_read);
954 if (ret) {
955 continue;
956 }
957 }
958
959 /* wait until the SD bus (CMD, DAT) is free or errors occur */
960 ret = rcar_mmc_poll_reg_flags_check_err(
961 dev, RCAR_MMC_INFO2, RCAR_MMC_INFO2_SCLKDIVEN, RCAR_MMC_INFO2_SCLKDIVEN,
962 true, false, MMC_POLL_FLAGS_TIMEOUT_US);
963 }
964
965 if (ret) {
966 rcar_mmc_reset(dev);
967 #ifdef CONFIG_RCAR_MMC_SCC_SUPPORT
968 rcar_mmc_retune_if_needed(dev, true);
969 #endif
970 }
971
972 dev_data->is_last_cmd_app_cmd = (cmd->opcode == SD_APP_CMD);
973
974 return ret;
975 }
976
977 /* convert sd_voltage to string */
rcar_mmc_get_signal_voltage_str(enum sd_voltage voltage)978 static inline const char *const rcar_mmc_get_signal_voltage_str(enum sd_voltage voltage)
979 {
980 static const char *const sig_vol_str[] = {
981 [0] = "Unset", [SD_VOL_3_3_V] = "3.3V", [SD_VOL_3_0_V] = "3.0V",
982 [SD_VOL_1_8_V] = "1.8V", [SD_VOL_1_2_V] = "1.2V",
983 };
984
985 if (voltage >= 0 && voltage < ARRAY_SIZE(sig_vol_str)) {
986 return sig_vol_str[voltage];
987 } else {
988 return "Unknown";
989 }
990 }
991
992 /* convert sdhc_timing_mode to string */
rcar_mmc_get_timing_str(enum sdhc_timing_mode timing)993 static inline const char *const rcar_mmc_get_timing_str(enum sdhc_timing_mode timing)
994 {
995 static const char *const timing_str[] = {
996 [0] = "Unset",
997 [SDHC_TIMING_LEGACY] = "LEGACY",
998 [SDHC_TIMING_HS] = "HS",
999 [SDHC_TIMING_SDR12] = "SDR12",
1000 [SDHC_TIMING_SDR25] = "SDR25",
1001 [SDHC_TIMING_SDR50] = "SDR50",
1002 [SDHC_TIMING_SDR104] = "SDR104",
1003 [SDHC_TIMING_DDR50] = "DDR50",
1004 [SDHC_TIMING_DDR52] = "DDR52",
1005 [SDHC_TIMING_HS200] = "HS200",
1006 [SDHC_TIMING_HS400] = "HS400",
1007 };
1008
1009 if (timing >= 0 && timing < ARRAY_SIZE(timing_str)) {
1010 return timing_str[timing];
1011 } else {
1012 return "Unknown";
1013 }
1014 }
1015
1016 /* change voltage of MMC */
rcar_mmc_change_voltage(const struct mmc_rcar_cfg * cfg,struct sdhc_io * host_io,struct sdhc_io * ios)1017 static int rcar_mmc_change_voltage(const struct mmc_rcar_cfg *cfg, struct sdhc_io *host_io,
1018 struct sdhc_io *ios)
1019 {
1020 int ret = 0;
1021
1022 /* Set host signal voltage */
1023 if (!ios->signal_voltage || ios->signal_voltage == host_io->signal_voltage) {
1024 return 0;
1025 }
1026
1027 switch (ios->signal_voltage) {
1028 case SD_VOL_3_3_V:
1029 ret = regulator_set_voltage(cfg->regulator_vqmmc, 3300000, 3300000);
1030 if (ret && ret != -ENOSYS) {
1031 break;
1032 }
1033
1034 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
1035 break;
1036 case SD_VOL_1_8_V:
1037 ret = regulator_set_voltage(cfg->regulator_vqmmc, 1800000, 1800000);
1038 if (ret && ret != -ENOSYS) {
1039 break;
1040 }
1041
1042 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_UHS);
1043 break;
1044 case SD_VOL_3_0_V:
1045 case SD_VOL_1_2_V:
1046 /* fall through */
1047 default:
1048 ret = -ENOTSUP;
1049 return ret;
1050 }
1051
1052 if (!ret) {
1053 host_io->signal_voltage = ios->signal_voltage;
1054 }
1055
1056 return ret;
1057 }
1058
1059 /* note: for zero val function returns zero */
round_up_next_pwr_of_2(uint32_t val)1060 static inline uint32_t round_up_next_pwr_of_2(uint32_t val)
1061 {
1062 __ASSERT(val, "Zero val passed to %s", __func__);
1063
1064 val--;
1065 val |= val >> 1;
1066 val |= val >> 2;
1067 val |= val >> 4;
1068 val |= val >> 8;
1069 val |= val >> 16;
1070 return ++val;
1071 }
1072
1073 /**
1074 * @brief configure clock divider on MMC controller
1075 *
1076 * @note In/out parameters should be checked by a caller function.
1077 * @note In the case of data transfer in HS400 mode (HS400 bit in
1078 * SDIF_MODE = 1), do not set this width equal to 1.
1079 * @note In the case of writing of one-byte block, 8-bit width cannot
1080 * be specified for the bus width. Change the bus width to 4 bits
1081 * or 1 bit before writing one-byte block.
1082 *
1083 * @param dev MMC device
1084 * @param io I/O properties
1085 *
1086 * @retval 0 I/O was configured correctly
1087 * @retval -ENOTSUP: controller does not support these I/O settings
1088 * @retval -ETIMEDOUT: card busy flag is set during long time
1089 */
rcar_mmc_set_clk_rate(const struct device * dev,struct sdhc_io * ios)1090 static int rcar_mmc_set_clk_rate(const struct device *dev, struct sdhc_io *ios)
1091 {
1092 int ret = 0;
1093 uint32_t divisor;
1094 uint32_t mmc_clk_ctl;
1095 struct mmc_rcar_data *data = dev->data;
1096 const struct mmc_rcar_cfg *cfg = dev->config;
1097 struct sdhc_io *host_io = &data->host_io;
1098
1099 if (host_io->clock == ios->clock) {
1100 return 0;
1101 }
1102
1103 if (ios->clock == 0) {
1104 host_io->clock = 0;
1105 return rcar_mmc_enable_clock(dev, false);
1106 }
1107
1108 if (ios->clock > data->props.f_max || ios->clock < data->props.f_min) {
1109 LOG_ERR("SDHC I/O: clock (%d) isn't in range %d - %d Hz", ios->clock,
1110 data->props.f_min, data->props.f_max);
1111 return -EINVAL;
1112 }
1113
1114 divisor = DIV_ROUND_UP(cfg->max_frequency, ios->clock);
1115
1116 /* Do not set divider to 0xff in DDR mode */
1117 if (data->ddr_mode && (divisor == 1)) {
1118 divisor = 2;
1119 }
1120
1121 divisor = round_up_next_pwr_of_2(divisor);
1122 if (divisor == 1) {
1123 divisor = RCAR_MMC_CLKCTL_RCAR_DIV1;
1124 } else {
1125 divisor >>= 2;
1126 }
1127
1128 /*
1129 * Stop the clock before changing its rate
1130 * to avoid a glitch signal
1131 */
1132 ret = rcar_mmc_enable_clock(dev, false);
1133 if (ret) {
1134 return ret;
1135 }
1136
1137 mmc_clk_ctl = rcar_mmc_read_reg32(dev, RCAR_MMC_CLKCTL);
1138 if ((mmc_clk_ctl & RCAR_MMC_CLKCTL_SCLKEN) &&
1139 (mmc_clk_ctl & RCAR_MMC_CLKCTL_DIV_MASK) == divisor) {
1140 host_io->clock = ios->clock;
1141 return rcar_mmc_enable_clock(dev, false);
1142 }
1143
1144 /*
1145 * Do not change the values of these bits
1146 * when the CBSY bit in SD_INFO2 is 1
1147 */
1148 ret = rcar_mmc_poll_reg_flags_check_err(dev, RCAR_MMC_INFO2, RCAR_MMC_INFO2_CBSY, 0, false,
1149 false, MMC_POLL_FLAGS_TIMEOUT_US);
1150 if (ret) {
1151 return -ETIMEDOUT;
1152 }
1153
1154 mmc_clk_ctl &= ~RCAR_MMC_CLKCTL_DIV_MASK;
1155 mmc_clk_ctl |= divisor;
1156
1157 rcar_mmc_write_reg32(dev, RCAR_MMC_CLKCTL, mmc_clk_ctl);
1158 ret = rcar_mmc_enable_clock(dev, true);
1159 if (ret) {
1160 return ret;
1161 }
1162
1163 host_io->clock = ios->clock;
1164
1165 LOG_DBG("%s: set clock rate to %d", dev->name, ios->clock);
1166
1167 return 0;
1168 }
1169
1170 /**
1171 * @brief set bus width of MMC
1172 *
1173 * @note In/out parameters should be checked by a caller function.
1174 * @note In the case of data transfer in HS400 mode (HS400 bit in
1175 * SDIF_MODE = 1), do not set this width equal to 1.
1176 * @note In the case of writing of one-byte block, 8-bit width cannot
1177 * be specified for the bus width. Change the bus width to 4 bits
1178 * or 1 bit before writing one-byte block.
1179 *
1180 * @param dev MMC device
1181 * @param io I/O properties
1182 *
1183 * @retval 0 I/O was configured correctly
1184 * @retval -ENOTSUP: controller does not support these I/O settings
1185 * @retval -ETIMEDOUT: card busy flag is set during long time
1186 */
rcar_mmc_set_bus_width(const struct device * dev,struct sdhc_io * ios)1187 static int rcar_mmc_set_bus_width(const struct device *dev, struct sdhc_io *ios)
1188 {
1189 int ret = 0;
1190 uint32_t mmc_option_reg;
1191 uint32_t reg_width;
1192 struct mmc_rcar_data *data = dev->data;
1193 struct sdhc_io *host_io = &data->host_io;
1194
1195 /* Set bus width */
1196 if (host_io->bus_width == ios->bus_width) {
1197 return 0;
1198 }
1199
1200 if (!ios->bus_width) {
1201 return 0;
1202 }
1203
1204 switch (ios->bus_width) {
1205 case SDHC_BUS_WIDTH1BIT:
1206 reg_width = RCAR_MMC_OPTION_WIDTH_1;
1207 break;
1208 case SDHC_BUS_WIDTH4BIT:
1209 if (data->props.host_caps.bus_4_bit_support) {
1210 reg_width = RCAR_MMC_OPTION_WIDTH_4;
1211 } else {
1212 LOG_ERR("SDHC I/O: 4-bits bus width isn't supported");
1213 return -ENOTSUP;
1214 }
1215 break;
1216 case SDHC_BUS_WIDTH8BIT:
1217 if (data->props.host_caps.bus_8_bit_support) {
1218 reg_width = RCAR_MMC_OPTION_WIDTH_8;
1219 } else {
1220 LOG_ERR("SDHC I/O: 8-bits bus width isn't supported");
1221 return -ENOTSUP;
1222 }
1223 break;
1224 default:
1225 return -ENOTSUP;
1226 }
1227
1228 /*
1229 * Do not change the values of these bits
1230 * when the CBSY bit in SD_INFO2 is 1
1231 */
1232 ret = rcar_mmc_poll_reg_flags_check_err(dev, RCAR_MMC_INFO2, RCAR_MMC_INFO2_CBSY, 0, false,
1233 false, MMC_POLL_FLAGS_TIMEOUT_US);
1234 if (ret) {
1235 return -ETIMEDOUT;
1236 }
1237
1238 mmc_option_reg = rcar_mmc_read_reg32(dev, RCAR_MMC_OPTION);
1239 mmc_option_reg &= ~RCAR_MMC_OPTION_WIDTH_MASK;
1240 mmc_option_reg |= reg_width;
1241 rcar_mmc_write_reg32(dev, RCAR_MMC_OPTION, mmc_option_reg);
1242
1243 host_io->bus_width = ios->bus_width;
1244
1245 LOG_DBG("%s: set bus-width to %d", dev->name, host_io->bus_width);
1246 return 0;
1247 }
1248
1249 /**
1250 * set DDR mode on MMC controller according to value inside
1251 * ddr_mode field from @ref mmc_rcar_data structure.
1252 */
rcar_mmc_set_ddr_mode(const struct device * dev)1253 static int rcar_mmc_set_ddr_mode(const struct device *dev)
1254 {
1255 int ret = 0;
1256 uint32_t if_mode_reg;
1257 struct mmc_rcar_data *data = dev->data;
1258
1259 /*
1260 * Do not change the values of these bits
1261 * when the CBSY bit in SD_INFO2 is 1
1262 */
1263 ret = rcar_mmc_poll_reg_flags_check_err(dev, RCAR_MMC_INFO2, RCAR_MMC_INFO2_CBSY, 0, false,
1264 false, MMC_POLL_FLAGS_TIMEOUT_US);
1265 if (ret) {
1266 return -ETIMEDOUT;
1267 }
1268
1269 if_mode_reg = rcar_mmc_read_reg32(dev, RCAR_MMC_IF_MODE);
1270 if (data->ddr_mode) {
1271 /* HS400 mode (DDR mode) */
1272 if_mode_reg |= RCAR_MMC_IF_MODE_DDR;
1273 } else {
1274 /* Normal mode (default, high speed, or SDR) */
1275 if_mode_reg &= ~RCAR_MMC_IF_MODE_DDR;
1276 }
1277 rcar_mmc_write_reg32(dev, RCAR_MMC_IF_MODE, if_mode_reg);
1278
1279 return 0;
1280 }
1281
1282 /**
1283 * @brief set timing property of MMC
1284 *
1285 * For now function only can enable DDR mode and call the function for
1286 * changing voltage. It is expectable that we change clock using another
1287 * I/O option.
1288 * @note In/out parameters should be checked by a caller function.
1289 *
1290 * @param dev MMC device
1291 * @param io I/O properties
1292 *
1293 * @retval 0 I/O was configured correctly
1294 * @retval -ENOTSUP: controller does not support these I/O settings
1295 * @retval -ETIMEDOUT: card busy flag is set during long time
1296 */
rcar_mmc_set_timings(const struct device * dev,struct sdhc_io * ios)1297 static int rcar_mmc_set_timings(const struct device *dev, struct sdhc_io *ios)
1298 {
1299 int ret;
1300 struct mmc_rcar_data *data = dev->data;
1301 struct sdhc_io *host_io = &data->host_io;
1302 enum sd_voltage new_voltage = host_io->signal_voltage;
1303
1304 if (host_io->timing == ios->timing) {
1305 return 0;
1306 }
1307
1308 if (!host_io->timing) {
1309 return 0;
1310 }
1311
1312 data->ddr_mode = 0;
1313
1314 switch (ios->timing) {
1315 case SDHC_TIMING_LEGACY:
1316 break;
1317 case SDHC_TIMING_HS:
1318 if (!data->props.host_caps.high_spd_support) {
1319 LOG_ERR("SDHC I/O: HS timing isn't supported");
1320 return -ENOTSUP;
1321 }
1322 break;
1323 case SDHC_TIMING_SDR12:
1324 case SDHC_TIMING_SDR25:
1325 case SDHC_TIMING_SDR50:
1326 break;
1327 case SDHC_TIMING_SDR104:
1328 if (!data->props.host_caps.sdr104_support) {
1329 LOG_ERR("SDHC I/O: SDR104 timing isn't supported");
1330 return -ENOTSUP;
1331 }
1332 break;
1333 case SDHC_TIMING_HS400:
1334 if (!data->props.host_caps.hs400_support) {
1335 LOG_ERR("SDHC I/O: HS400 timing isn't supported");
1336 return -ENOTSUP;
1337 }
1338 new_voltage = SD_VOL_1_8_V;
1339 data->ddr_mode = 1;
1340 break;
1341 case SDHC_TIMING_DDR50:
1342 case SDHC_TIMING_DDR52:
1343 if (!data->props.host_caps.ddr50_support) {
1344 LOG_ERR("SDHC I/O: DDR50/DDR52 timing isn't supported");
1345 return -ENOTSUP;
1346 }
1347 data->ddr_mode = 1;
1348 break;
1349 case SDHC_TIMING_HS200:
1350 if (!data->props.host_caps.hs200_support) {
1351 LOG_ERR("SDHC I/O: HS200 timing isn't supported");
1352 return -ENOTSUP;
1353 }
1354 new_voltage = SD_VOL_1_8_V;
1355 break;
1356 default:
1357 return -ENOTSUP;
1358 }
1359
1360 ios->signal_voltage = new_voltage;
1361 if (rcar_mmc_change_voltage(dev->config, host_io, ios)) {
1362 return -ENOTSUP;
1363 }
1364
1365 ret = rcar_mmc_set_ddr_mode(dev);
1366 if (ret) {
1367 return ret;
1368 }
1369
1370 host_io->timing = ios->timing;
1371 return 0;
1372 }
1373
1374 /**
1375 * @brief set I/O properties of MMC
1376 *
1377 * I/O properties should be reconfigured when the card has been sent a command
1378 * to change its own MMC settings. This function can also be used to toggle
1379 * power to the SD card.
1380 *
1381 * @param dev MMC device
1382 * @param io I/O properties
1383 *
1384 * @retval 0 I/O was configured correctly
1385 * @retval -ENOTSUP: controller does not support these I/O settings
1386 * @retval -EINVAL: some of pointers provided to the function are NULL
1387 * @retval -ETIMEDOUT: card busy flag is set during long time
1388 */
rcar_mmc_set_io(const struct device * dev,struct sdhc_io * ios)1389 static int rcar_mmc_set_io(const struct device *dev, struct sdhc_io *ios)
1390 {
1391 int ret = 0;
1392 struct mmc_rcar_data *data;
1393 struct sdhc_io *host_io;
1394
1395 if (!dev || !ios || !dev->data || !dev->config) {
1396 return -EINVAL;
1397 }
1398
1399 data = dev->data;
1400 host_io = &data->host_io;
1401
1402 LOG_DBG("SDHC I/O: bus width %d, clock %dHz, card power %s, "
1403 "timing %s, voltage %s",
1404 ios->bus_width, ios->clock, ios->power_mode == SDHC_POWER_ON ? "ON" : "OFF",
1405 rcar_mmc_get_timing_str(ios->timing),
1406 rcar_mmc_get_signal_voltage_str(ios->signal_voltage));
1407
1408 /* Set host clock */
1409 ret = rcar_mmc_set_clk_rate(dev, ios);
1410 if (ret) {
1411 LOG_ERR("SDHC I/O: can't change clock rate error %d old %d new %d", ret,
1412 host_io->clock, ios->clock);
1413 return ret;
1414 }
1415
1416 /*
1417 * Set card bus mode
1418 *
1419 * SD Specifications Part 1 Physical Layer Simplified Specification Version 9.00
1420 * 4.7.1 Command Types: "... there is no Open Drain mode in SD Memory Card"
1421 *
1422 * The use of open-drain mode is not possible in SD memory cards because the SD bus uses
1423 * push-pull signaling, where both the host and the card can actively drive the data lines
1424 * high or low.
1425 * In an SD card, the command and response signaling needs to be bidirectional, and each
1426 * signal line needs to be actively driven high or low. The use of open-drain mode in this
1427 * scenario would not allow for the necessary bidirectional signaling and could result in
1428 * communication errors.
1429 *
1430 * JEDEC Standard No. 84-B51, 10 The eMMC bus:
1431 * "The e•MMC bus has eleven communication lines:
1432 * - CMD: Command is a bidirectional signal. The host and Device drivers are operating in
1433 * two modes, open drain and push/pull.
1434 * - DAT0-7: Data lines are bidirectional signals. Host and Device drivers are operating
1435 * in push-pull mode.
1436 * - CLK: Clock is a host to Device signal. CLK operates in push-pull mode.
1437 * - Data Strobe: Data Strobe is a Device to host signal. Data Strobe operates in
1438 * push-pull mode."
1439 *
1440 * So, open-drain mode signaling is supported in eMMC as one of the signaling modes for
1441 * the CMD line. But Gen3 and Gen4 boards has MMC/SD controller which is a specialized
1442 * component designed specifically for managing communication with MMC/SD devices. It
1443 * handles low-level operations such as protocol handling, data transfer, and error
1444 * checking and should take care of the low-level details of communicating with the
1445 * MMC/SD card, including setting the bus mode. Moreover, we can use only MMIO mode, the
1446 * processor communicates with the MMC/SD controller through memory read and write
1447 * operations, rather than through dedicated I/O instructions or specialized data transfer
1448 * protocols like SPI or SDIO. Finally, R-Car Gen3 and Gen4 "User’s manuals: Hardware"
1449 * don't have direct configurations for open-drain mode for both PFC and GPIO and Zephyr
1450 * SDHC subsystem doesn't support any bus mode except push-pull.
1451 */
1452 if (ios->bus_mode != SDHC_BUSMODE_PUSHPULL) {
1453 LOG_ERR("SDHC I/O: not supported bus mode %d", ios->bus_mode);
1454 return -ENOTSUP;
1455 }
1456 host_io->bus_mode = ios->bus_mode;
1457
1458 /* Set card power */
1459 if (ios->power_mode && host_io->power_mode != ios->power_mode) {
1460 const struct mmc_rcar_cfg *cfg = dev->config;
1461
1462 switch (ios->power_mode) {
1463 case SDHC_POWER_ON:
1464 ret = regulator_enable(cfg->regulator_vmmc);
1465 if (ret) {
1466 break;
1467 }
1468
1469 k_msleep(data->props.power_delay);
1470
1471 ret = regulator_enable(cfg->regulator_vqmmc);
1472 if (ret) {
1473 break;
1474 }
1475
1476 k_msleep(data->props.power_delay);
1477 ret = rcar_mmc_enable_clock(dev, true);
1478 break;
1479 case SDHC_POWER_OFF:
1480 if (regulator_is_enabled(cfg->regulator_vqmmc)) {
1481 ret = regulator_disable(cfg->regulator_vqmmc);
1482 if (ret) {
1483 break;
1484 }
1485 }
1486
1487 if (regulator_is_enabled(cfg->regulator_vmmc)) {
1488 ret = regulator_disable(cfg->regulator_vmmc);
1489 if (ret) {
1490 break;
1491 }
1492 }
1493
1494 ret = rcar_mmc_enable_clock(dev, false);
1495 break;
1496 default:
1497 LOG_ERR("SDHC I/O: not supported power mode %d", ios->power_mode);
1498 return -ENOTSUP;
1499 }
1500
1501 if (ret) {
1502 return ret;
1503 }
1504 host_io->power_mode = ios->power_mode;
1505 }
1506
1507 ret = rcar_mmc_set_bus_width(dev, ios);
1508 if (ret) {
1509 LOG_ERR("SDHC I/O: can't change bus width error %d old %d new %d", ret,
1510 host_io->bus_width, ios->bus_width);
1511 return ret;
1512 }
1513
1514 ret = rcar_mmc_set_timings(dev, ios);
1515 if (ret) {
1516 LOG_ERR("SDHC I/O: can't change timing error %d old %d new %d", ret,
1517 host_io->timing, ios->timing);
1518 return ret;
1519 }
1520
1521 ret = rcar_mmc_change_voltage(dev->config, host_io, ios);
1522 if (ret) {
1523 LOG_ERR("SDHC I/O: can't change voltage! error %d old %d new %d", ret,
1524 host_io->signal_voltage, ios->signal_voltage);
1525 return ret;
1526 }
1527
1528 return 0;
1529 }
1530
1531 /**
1532 * @brief check for MMC card presence
1533 *
1534 * Checks if card is present on the bus.
1535 *
1536 * @param dev MMC device
1537 *
1538 * @retval 1 card is present
1539 * @retval 0 card is not present
1540 * @retval -EINVAL: some of pointers provided to the function are NULL
1541 */
rcar_mmc_get_card_present(const struct device * dev)1542 static int rcar_mmc_get_card_present(const struct device *dev)
1543 {
1544 const struct mmc_rcar_cfg *cfg;
1545
1546 if (!dev || !dev->config) {
1547 return -EINVAL;
1548 }
1549
1550 cfg = dev->config;
1551 if (cfg->non_removable) {
1552 return 1;
1553 }
1554
1555 return !!(rcar_mmc_read_reg32(dev, RCAR_MMC_INFO1) & RCAR_MMC_INFO1_CD);
1556 }
1557
1558 #ifdef CONFIG_RCAR_MMC_SCC_SUPPORT
1559
1560 /* JESD84-B51, 6.6.5.1 Sampling Tuning Sequence for HS200 */
1561 static const uint8_t tun_block_8_bits_bus[] = {
1562 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
1563 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
1564 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
1565 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
1566 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
1567 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
1568 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
1569 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
1570 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
1571 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
1572 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
1573 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
1574 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
1575 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
1576 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
1577 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
1578 };
1579
1580 /*
1581 * In 4 bit mode the same pattern is used as shown above,
1582 * but only first 4 bits least significant from every byte is used, examle:
1583 * 8-bits pattern: 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00 ...
1584 * f f 0 f f f 0 0 ...
1585 * 4-bits pattern: 0xff 0x0f 0xff 0x00 ...
1586 */
1587 static const uint8_t tun_block_4_bits_bus[] = {
1588 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
1589 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
1590 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
1591 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
1592 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
1593 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
1594 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
1595 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
1596 };
1597
1598 #define RENESAS_TAPNUM 8
1599
1600 /**
1601 * @brief run MMC tuning
1602 *
1603 * MMC cards require signal tuning for UHS modes SDR104, HS200 or HS400.
1604 * This function allows an application to request the SD host controller
1605 * to tune the card.
1606 *
1607 * @param dev MMC device
1608 *
1609 * @retval 0 tuning succeeded (card is ready for commands), otherwise negative number is returned
1610 */
rcar_mmc_execute_tuning(const struct device * dev)1611 static int rcar_mmc_execute_tuning(const struct device *dev)
1612 {
1613 int ret = -ENOTSUP;
1614 const uint8_t *tun_block_ptr;
1615 uint8_t tap_idx;
1616 uint8_t is_mmc_cmd = false;
1617 struct sdhc_command cmd = {0};
1618 struct sdhc_data data = {0};
1619 struct mmc_rcar_data *dev_data;
1620 uint16_t valid_taps = 0;
1621 uint16_t smpcmp_bitmask = 0;
1622
1623 BUILD_ASSERT(sizeof(valid_taps) * 8 >= 2 * RENESAS_TAPNUM);
1624 BUILD_ASSERT(sizeof(smpcmp_bitmask) * 8 >= 2 * RENESAS_TAPNUM);
1625
1626 if (!dev) {
1627 return -EINVAL;
1628 }
1629
1630 dev_data = dev->data;
1631 dev_data->can_retune = 0;
1632
1633 if (dev_data->host_io.timing == SDHC_TIMING_HS200) {
1634 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1635 is_mmc_cmd = true;
1636 } else if (dev_data->host_io.timing != SDHC_TIMING_HS400) {
1637 cmd.opcode = SD_SEND_TUNING_BLOCK;
1638 } else {
1639 LOG_ERR("%s: tuning isn't possible in HS400 mode, it should be done in HS200",
1640 dev->name);
1641 return -EINVAL;
1642 }
1643
1644 cmd.response_type = SD_RSP_TYPE_R1;
1645 cmd.timeout_ms = CONFIG_SD_CMD_TIMEOUT;
1646
1647 data.blocks = 1;
1648 data.data = dev_data->tuning_buf;
1649 data.timeout_ms = CONFIG_SD_DATA_TIMEOUT;
1650 if (dev_data->host_io.bus_width == SDHC_BUS_WIDTH4BIT) {
1651 data.block_size = sizeof(tun_block_4_bits_bus);
1652 tun_block_ptr = tun_block_4_bits_bus;
1653 } else if (dev_data->host_io.bus_width == SDHC_BUS_WIDTH8BIT) {
1654 data.block_size = sizeof(tun_block_8_bits_bus);
1655 tun_block_ptr = tun_block_8_bits_bus;
1656 } else {
1657 LOG_ERR("%s: don't support tuning for 1-bit bus width", dev->name);
1658 return -EINVAL;
1659 }
1660
1661 ret = rcar_mmc_enable_clock(dev, false);
1662 if (ret) {
1663 return ret;
1664 }
1665
1666 /* enable modes SDR104/HS200/HS400 */
1667 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_DT2FF, 0x300);
1668 /* SCC sampling clock operation is enabled */
1669 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_DTCNTL,
1670 RENESAS_SDHI_SCC_DTCNTL_TAPEN | RENESAS_TAPNUM << 16);
1671 /* SCC sampling clock is used */
1672 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_CKSEL, RENESAS_SDHI_SCC_CKSEL_DTSEL);
1673 /* SCC sampling clock position correction is disabled */
1674 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_RVSCNTL, 0);
1675 /* cleanup errors */
1676 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_RVSREQ, 0);
1677
1678 ret = rcar_mmc_enable_clock(dev, true);
1679 if (ret) {
1680 return ret;
1681 }
1682
1683 /*
1684 * two runs is better for detecting TAP ok cases like next:
1685 * - one burn: 0b10000011
1686 * - two burns: 0b1000001110000011
1687 * it is more easly to detect 3 OK taps in a row
1688 */
1689 for (tap_idx = 0; tap_idx < 2 * RENESAS_TAPNUM; tap_idx++) {
1690 /* clear flags */
1691 rcar_mmc_reset_and_mask_irqs(dev);
1692 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_TAPSET, tap_idx % RENESAS_TAPNUM);
1693 memset(dev_data->tuning_buf, 0, data.block_size);
1694 ret = rcar_mmc_request(dev, &cmd, &data);
1695 if (ret) {
1696 LOG_DBG("%s: received an error (%d) during tuning request", dev->name, ret);
1697
1698 if (is_mmc_cmd) {
1699 struct sdhc_command stop_cmd = {
1700 .opcode = SD_STOP_TRANSMISSION,
1701 .response_type = SD_RSP_TYPE_R1b,
1702 .timeout_ms = CONFIG_SD_CMD_TIMEOUT,
1703 };
1704
1705 rcar_mmc_request(dev, &stop_cmd, NULL);
1706 }
1707 continue;
1708 }
1709
1710 smpcmp_bitmask |= !rcar_mmc_read_reg32(dev, RENESAS_SDHI_SCC_SMPCMP) << tap_idx;
1711
1712 if (memcmp(tun_block_ptr, dev_data->tuning_buf, data.block_size)) {
1713 LOG_DBG("%s: received tuning block doesn't equal to pattert TAP index %u",
1714 dev->name, tap_idx);
1715 continue;
1716 }
1717
1718 valid_taps |= BIT(tap_idx);
1719
1720 LOG_DBG("%s: smpcmp_bitmask[%u] 0x%08x", dev->name, tap_idx, smpcmp_bitmask);
1721 }
1722
1723 /* both parts of bitmasks have to be the same */
1724 valid_taps &= (valid_taps >> RENESAS_TAPNUM);
1725 valid_taps |= (valid_taps << RENESAS_TAPNUM);
1726
1727 smpcmp_bitmask &= (smpcmp_bitmask >> RENESAS_TAPNUM);
1728 smpcmp_bitmask |= (smpcmp_bitmask << RENESAS_TAPNUM);
1729
1730 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_RVSREQ, 0);
1731
1732 if (!valid_taps) {
1733 LOG_ERR("%s: there isn't any valid tap during tuning", dev->name);
1734 goto reset_scc;
1735 }
1736
1737 /*
1738 * If all of the taps[i] is OK, the sampling clock position is selected by identifying
1739 * the change point of data. Change point of the data can be found in the value of
1740 * SCC_SMPCMP register
1741 */
1742 if ((valid_taps >> RENESAS_TAPNUM) == (1 << RENESAS_TAPNUM) - 1) {
1743 valid_taps = smpcmp_bitmask;
1744 }
1745
1746 /* do we have 3 set bits in a row at least */
1747 if (valid_taps & (valid_taps >> 1) & (valid_taps >> 2)) {
1748 uint32_t max_len_range_pos = 0;
1749 uint32_t max_bits_in_range = 0;
1750 uint32_t pos_of_lsb_set = 0;
1751
1752 /* all bits are set */
1753 if ((valid_taps >> RENESAS_TAPNUM) == (1 << RENESAS_TAPNUM) - 1) {
1754 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_TAPSET, 0);
1755
1756 if (!dev_data->manual_retuning) {
1757 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_RVSCNTL, 1);
1758 }
1759 dev_data->can_retune = 1;
1760 return 0;
1761 }
1762
1763 /* searching the longest range of set bits */
1764 while (valid_taps) {
1765 uint32_t num_bits_in_range;
1766 uint32_t rsh = 0;
1767
1768 rsh = find_lsb_set(valid_taps) - 1;
1769 pos_of_lsb_set += rsh;
1770
1771 /* shift all leading zeros */
1772 valid_taps >>= rsh;
1773
1774 num_bits_in_range = find_lsb_set(~valid_taps) - 1;
1775
1776 /* shift all leading ones */
1777 valid_taps >>= num_bits_in_range;
1778
1779 if (max_bits_in_range < num_bits_in_range) {
1780 max_bits_in_range = num_bits_in_range;
1781 max_len_range_pos = pos_of_lsb_set;
1782 }
1783 pos_of_lsb_set += num_bits_in_range;
1784 }
1785
1786 tap_idx = (max_len_range_pos + max_bits_in_range / 2) % RENESAS_TAPNUM;
1787 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_TAPSET, tap_idx);
1788
1789 LOG_DBG("%s: valid_taps %08x smpcmp_bitmask %08x tap_idx %u", dev->name, valid_taps,
1790 smpcmp_bitmask, tap_idx);
1791
1792 if (!dev_data->manual_retuning) {
1793 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_RVSCNTL, 1);
1794 }
1795 dev_data->can_retune = 1;
1796 return 0;
1797 }
1798
1799 reset_scc:
1800 rcar_mmc_disable_scc(dev);
1801 return ret;
1802 }
1803
1804 /* retune SCC in case of error during xref */
rcar_mmc_retune_if_needed(const struct device * dev,bool request_retune)1805 static int rcar_mmc_retune_if_needed(const struct device *dev, bool request_retune)
1806 {
1807 struct mmc_rcar_data *dev_data = dev->data;
1808 int ret = 0;
1809 uint32_t reg;
1810 bool scc_pos_err = false;
1811 uint8_t scc_tapset;
1812
1813 if (!dev_data->can_retune) {
1814 return 0;
1815 }
1816
1817 reg = rcar_mmc_read_reg32(dev, RENESAS_SDHI_SCC_RVSREQ);
1818 if (reg & RENESAS_SDHI_SCC_RVSREQ_ERR) {
1819 scc_pos_err = true;
1820 }
1821
1822 scc_tapset = rcar_mmc_read_reg32(dev, RENESAS_SDHI_SCC_TAPSET);
1823
1824 LOG_DBG("%s: scc_tapset %08x scc_rvsreq %08x request %d is manual tuning %d", dev->name,
1825 scc_tapset, reg, request_retune, dev_data->manual_retuning);
1826
1827 if (request_retune || (scc_pos_err && !dev_data->manual_retuning)) {
1828 return rcar_mmc_execute_tuning(dev);
1829 }
1830
1831 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_RVSREQ, 0);
1832
1833 switch (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAP_MASK) {
1834 case RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN:
1835 scc_tapset = (scc_tapset - 1) % RENESAS_TAPNUM;
1836 break;
1837 case RENESAS_SDHI_SCC_RVSREQ_REQTAPUP:
1838 scc_tapset = (scc_tapset + 1) % RENESAS_TAPNUM;
1839 break;
1840 default:
1841 ret = -EINVAL;
1842 LOG_ERR("%s: can't perform manual tuning SCC_RVSREQ %08x", dev->name, reg);
1843 break;
1844 }
1845
1846 if (!ret) {
1847 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_TAPSET, scc_tapset);
1848 }
1849
1850 return ret;
1851 }
1852
1853 #endif /* CONFIG_RCAR_MMC_SCC_SUPPORT */
1854
1855 /**
1856 * @brief Get MMC controller properties
1857 *
1858 * Gets host properties from the host controller. Host controller should
1859 * initialize all values in the @ref sdhc_host_props structure provided.
1860 *
1861 * @param dev Renesas MMC device
1862 * @param props property structure to be filled by MMC driver
1863 *
1864 * @retval 0 function succeeded.
1865 * @retval -EINVAL: some of pointers provided to the function are NULL
1866 */
rcar_mmc_get_host_props(const struct device * dev,struct sdhc_host_props * props)1867 static int rcar_mmc_get_host_props(const struct device *dev, struct sdhc_host_props *props)
1868 {
1869 struct mmc_rcar_data *data;
1870
1871 if (!props || !dev || !dev->data) {
1872 return -EINVAL;
1873 }
1874
1875 data = dev->data;
1876 memcpy(props, &data->props, sizeof(*props));
1877 return 0;
1878 }
1879
1880 static DEVICE_API(sdhc, rcar_sdhc_api) = {
1881 .card_busy = rcar_mmc_card_busy,
1882 #ifdef CONFIG_RCAR_MMC_SCC_SUPPORT
1883 .execute_tuning = rcar_mmc_execute_tuning,
1884 #endif
1885 .get_card_present = rcar_mmc_get_card_present,
1886 .get_host_props = rcar_mmc_get_host_props,
1887 .request = rcar_mmc_request,
1888 .reset = rcar_mmc_reset,
1889 .set_io = rcar_mmc_set_io,
1890 };
1891
1892 /* start SD-IF clock at max frequency configured in dts */
rcar_mmc_init_start_clk(const struct mmc_rcar_cfg * cfg)1893 static int rcar_mmc_init_start_clk(const struct mmc_rcar_cfg *cfg)
1894 {
1895 int ret = 0;
1896 const struct device *cpg_dev = cfg->cpg_dev;
1897 uintptr_t rate = cfg->max_frequency;
1898
1899 ret = clock_control_on(cpg_dev, (clock_control_subsys_t *)&cfg->bus_clk);
1900 if (ret < 0) {
1901 return ret;
1902 }
1903
1904 ret = clock_control_on(cpg_dev, (clock_control_subsys_t *)&cfg->cpg_clk);
1905 if (ret < 0) {
1906 return ret;
1907 }
1908
1909 ret = clock_control_set_rate(cpg_dev, (clock_control_subsys_t *)&cfg->cpg_clk,
1910 (clock_control_subsys_rate_t)rate);
1911 if (ret < 0) {
1912 clock_control_off(cpg_dev, (clock_control_subsys_t *)&cfg->cpg_clk);
1913 }
1914
1915 rate = MMC_BUS_CLOCK_FREQ;
1916 ret = clock_control_set_rate(cpg_dev, (clock_control_subsys_t *)&cfg->bus_clk,
1917 (clock_control_subsys_rate_t)rate);
1918 /* SD spec recommends at least 1 ms of delay after start of clock */
1919 k_msleep(1);
1920
1921 return ret;
1922 }
1923
rcar_mmc_init_host_props(const struct device * dev)1924 static void rcar_mmc_init_host_props(const struct device *dev)
1925 {
1926 struct mmc_rcar_data *data = dev->data;
1927 const struct mmc_rcar_cfg *cfg = dev->config;
1928 struct sdhc_host_props *props = &data->props;
1929 struct sdhc_host_caps *host_caps = &props->host_caps;
1930
1931 memset(props, 0, sizeof(*props));
1932
1933 /* Note: init only properties that are used for mmc/sdhc */
1934
1935 props->f_max = cfg->max_frequency;
1936 /*
1937 * note: actually, it's possible to get lower frequency
1938 * if we use divider from cpg too
1939 */
1940 props->f_min = (cfg->max_frequency >> 9);
1941
1942 props->power_delay = 100; /* ms */
1943
1944 props->is_spi = 0;
1945
1946 switch (cfg->bus_width) {
1947 case SDHC_BUS_WIDTH8BIT:
1948 host_caps->bus_8_bit_support = 1;
1949 case SDHC_BUS_WIDTH4BIT:
1950 host_caps->bus_4_bit_support = 1;
1951 default:
1952 break;
1953 }
1954
1955 host_caps->high_spd_support = 1;
1956 #ifdef CONFIG_RCAR_MMC_SCC_SUPPORT
1957 host_caps->sdr104_support = cfg->mmc_sdr104_support;
1958 host_caps->sdr50_support = cfg->uhs_support;
1959 /* neither Linux nor U-boot support DDR50 mode, that's why we don't support it too */
1960 host_caps->ddr50_support = 0;
1961 host_caps->hs200_support = cfg->mmc_hs200_1_8v;
1962 /* TODO: add support */
1963 host_caps->hs400_support = 0;
1964 #endif
1965
1966 host_caps->vol_330_support =
1967 regulator_is_supported_voltage(cfg->regulator_vqmmc, 3300000, 3300000);
1968 host_caps->vol_300_support =
1969 regulator_is_supported_voltage(cfg->regulator_vqmmc, 3000000, 3000000);
1970 host_caps->vol_180_support =
1971 regulator_is_supported_voltage(cfg->regulator_vqmmc, 1800000, 1800000);
1972 }
1973
1974 /* reset sampling clock controller registers */
rcar_mmc_disable_scc(const struct device * dev)1975 static int rcar_mmc_disable_scc(const struct device *dev)
1976 {
1977 int ret;
1978 uint32_t reg;
1979 struct mmc_rcar_data *data = dev->data;
1980 uint32_t mmc_clk_ctl = rcar_mmc_read_reg32(dev, RCAR_MMC_CLKCTL);
1981
1982 /* just to be to be sure that the SD clock is disabled */
1983 ret = rcar_mmc_enable_clock(dev, false);
1984 if (ret) {
1985 return ret;
1986 }
1987
1988 /*
1989 * Reset SCC registers, need to disable and enable clock
1990 * before and after reset
1991 */
1992
1993 /* Disable SCC sampling clock */
1994 reg = rcar_mmc_read_reg32(dev, RENESAS_SDHI_SCC_CKSEL);
1995 reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
1996 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_CKSEL, reg);
1997
1998 /* disable hs400 mode & data output timing */
1999 reg = rcar_mmc_read_reg32(dev, RENESAS_SDHI_SCC_TMPPORT2);
2000 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN | RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
2001 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_TMPPORT2, reg);
2002
2003 ret = rcar_mmc_enable_clock(dev, (mmc_clk_ctl & RCAR_MMC_CLKCTL_OFFEN) ? false : true);
2004 if (ret) {
2005 return ret;
2006 }
2007
2008 /* disable SCC sampling clock position correction */
2009 reg = rcar_mmc_read_reg32(dev, RENESAS_SDHI_SCC_RVSCNTL);
2010 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
2011 rcar_mmc_write_reg32(dev, RENESAS_SDHI_SCC_RVSCNTL, reg);
2012
2013 data->can_retune = 0;
2014
2015 return 0;
2016 }
2017
2018 /* initialize and configure the Renesas MMC controller registers */
rcar_mmc_init_controller_regs(const struct device * dev)2019 static int rcar_mmc_init_controller_regs(const struct device *dev)
2020 {
2021 int ret = 0;
2022 uint32_t reg;
2023 struct mmc_rcar_data *data = dev->data;
2024 struct sdhc_io ios = {0};
2025
2026 rcar_mmc_reset(dev);
2027
2028 /* Disable SD clock (SD_CLK) output */
2029 ret = rcar_mmc_enable_clock(dev, false);
2030 if (ret) {
2031 return ret;
2032 }
2033
2034 /* set transfer data length to 0 */
2035 rcar_mmc_write_reg32(dev, RCAR_MMC_SIZE, 0);
2036
2037 /* disable the SD_BUF read/write DMA transfer */
2038 reg = rcar_mmc_read_reg32(dev, RCAR_MMC_EXTMODE);
2039 reg &= ~RCAR_MMC_EXTMODE_DMA_EN;
2040 rcar_mmc_write_reg32(dev, RCAR_MMC_EXTMODE, reg);
2041 /* mask DMA irqs and clear dma irq flags */
2042 rcar_mmc_reset_and_mask_irqs(dev);
2043 /* set system address increment mode selector & 64-bit bus width */
2044 reg = rcar_mmc_read_reg32(dev, RCAR_MMC_DMA_MODE);
2045 reg |= RCAR_MMC_DMA_MODE_ADDR_INC | RCAR_MMC_DMA_MODE_WIDTH;
2046 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_MODE, reg);
2047
2048 /* store version of introductory IP */
2049 data->ver = rcar_mmc_read_reg32(dev, RCAR_MMC_VERSION);
2050 data->ver &= RCAR_MMC_VERSION_IP;
2051
2052 /*
2053 * set bus width to 1
2054 * timeout counter: SDCLK * 2^27
2055 * card detect time counter: SDϕ * 2^24
2056 */
2057 reg = rcar_mmc_read_reg32(dev, RCAR_MMC_OPTION);
2058 reg |= RCAR_MMC_OPTION_WIDTH_MASK | 0xEE;
2059 rcar_mmc_write_reg32(dev, RCAR_MMC_OPTION, reg);
2060
2061 /* block count enable */
2062 rcar_mmc_write_reg32(dev, RCAR_MMC_STOP, RCAR_MMC_STOP_SEC);
2063 /* number of transfer blocks */
2064 rcar_mmc_write_reg32(dev, RCAR_MMC_SECCNT, 0);
2065
2066 /*
2067 * SD_BUF0 data swap disabled.
2068 * Read/write access to SD_BUF0 can be performed with the 64-bit access.
2069 *
2070 * Note: when using the DMA, the bus width should be fixed at 64 bits.
2071 */
2072 rcar_mmc_write_reg32(dev, RCAR_MMC_HOST_MODE, 0);
2073 data->width_access_sd_buf0 = 8;
2074
2075 /* disable sampling clock controller, it is used for uhs/sdr104, hs200 and hs400 */
2076 ret = rcar_mmc_disable_scc(dev);
2077 if (ret) {
2078 return ret;
2079 }
2080
2081 /*
2082 * configure divider inside MMC controller
2083 * set maximum possible divider
2084 */
2085 ios.clock = data->props.f_min;
2086 rcar_mmc_set_clk_rate(dev, &ios);
2087
2088 data->restore_cfg_after_reset = 1;
2089
2090 return 0;
2091 }
2092
2093 #ifdef CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT
rcar_mmc_irq_handler(const void * arg)2094 static void rcar_mmc_irq_handler(const void *arg)
2095 {
2096 const struct device *dev = arg;
2097
2098 uint32_t dma_info1 = rcar_mmc_read_reg32(dev, RCAR_MMC_DMA_INFO1);
2099 uint32_t dma_info2 = rcar_mmc_read_reg32(dev, RCAR_MMC_DMA_INFO2);
2100
2101 if (dma_info1 || dma_info2) {
2102 struct mmc_rcar_data *data = dev->data;
2103
2104 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO1_MASK, 0xfffffeff);
2105 rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO2_MASK, ~0);
2106 k_sem_give(&data->irq_xref_fin);
2107 } else {
2108 LOG_WRN("%s: warning: non-dma event triggers irq", dev->name);
2109 }
2110 }
2111 #endif /* CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT */
2112
2113 /* initialize and configure the Renesas MMC driver */
rcar_mmc_init(const struct device * dev)2114 static int rcar_mmc_init(const struct device *dev)
2115 {
2116 int ret = 0;
2117 struct mmc_rcar_data *data = dev->data;
2118 const struct mmc_rcar_cfg *cfg = dev->config;
2119
2120 #ifdef CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT
2121 ret = k_sem_init(&data->irq_xref_fin, 0, 1);
2122 if (ret) {
2123 LOG_ERR("%s: can't init semaphore", dev->name);
2124 return ret;
2125 }
2126 #endif
2127
2128 DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
2129
2130 /* Configure dt provided device signals when available */
2131 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
2132 if (ret < 0) {
2133 LOG_ERR("%s: error can't apply pinctrl state", dev->name);
2134 goto exit_unmap;
2135 }
2136
2137 if (!device_is_ready(cfg->cpg_dev)) {
2138 LOG_ERR("%s: error cpg_dev isn't ready", dev->name);
2139 ret = -ENODEV;
2140 goto exit_unmap;
2141 }
2142
2143 ret = rcar_mmc_init_start_clk(cfg);
2144 if (ret < 0) {
2145 LOG_ERR("%s: error can't turn on the cpg", dev->name);
2146 goto exit_unmap;
2147 }
2148
2149 /* it's needed for SDHC */
2150 rcar_mmc_init_host_props(dev);
2151
2152 ret = rcar_mmc_init_controller_regs(dev);
2153 if (ret) {
2154 goto exit_disable_clk;
2155 }
2156
2157 #ifdef CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT
2158 cfg->irq_config_func(dev);
2159 #endif /* CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT */
2160
2161 LOG_INF("%s: initialize driver, MMC version 0x%hhx", dev->name, data->ver);
2162
2163 return 0;
2164
2165 exit_disable_clk:
2166 clock_control_off(cfg->cpg_dev, (clock_control_subsys_t *)&cfg->cpg_clk);
2167
2168 exit_unmap:
2169 #if defined(DEVICE_MMIO_IS_IN_RAM) && defined(CONFIG_MMU)
2170 k_mem_unmap_phys_bare((uint8_t *)DEVICE_MMIO_GET(dev), DEVICE_MMIO_ROM_PTR(dev)->size);
2171 #endif
2172 return ret;
2173 }
2174
2175 #ifdef CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT
2176 #define RCAR_MMC_CONFIG_FUNC(n) \
2177 static void irq_config_func_##n(const struct device *dev) \
2178 { \
2179 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), rcar_mmc_irq_handler, \
2180 DEVICE_DT_INST_GET(n), DT_INST_IRQ(n, flags)); \
2181 irq_enable(DT_INST_IRQN(n)); \
2182 }
2183 #define RCAR_MMC_IRQ_CFG_FUNC_INIT(n) .irq_config_func = irq_config_func_##n,
2184 #else
2185 #define RCAR_MMC_IRQ_CFG_FUNC_INIT(n)
2186 #define RCAR_MMC_CONFIG_FUNC(n)
2187 #endif
2188
2189 #define RCAR_MMC_INIT(n) \
2190 static struct mmc_rcar_data mmc_rcar_data_##n; \
2191 PINCTRL_DT_INST_DEFINE(n); \
2192 RCAR_MMC_CONFIG_FUNC(n); \
2193 static const struct mmc_rcar_cfg mmc_rcar_cfg_##n = { \
2194 DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \
2195 .cpg_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
2196 .cpg_clk.module = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
2197 .cpg_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
2198 .bus_clk.module = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, module), \
2199 .bus_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, domain), \
2200 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
2201 .regulator_vqmmc = DEVICE_DT_GET(DT_PHANDLE(DT_DRV_INST(n), vqmmc_supply)), \
2202 .regulator_vmmc = DEVICE_DT_GET(DT_PHANDLE(DT_DRV_INST(n), vmmc_supply)), \
2203 .max_frequency = DT_INST_PROP(n, max_bus_freq), \
2204 .non_removable = DT_INST_PROP(n, non_removable), \
2205 .mmc_hs200_1_8v = DT_INST_PROP(n, mmc_hs200_1_8v), \
2206 .mmc_hs400_1_8v = DT_INST_PROP(n, mmc_hs400_1_8v), \
2207 .mmc_sdr104_support = DT_INST_PROP(n, mmc_sdr104_support), \
2208 .uhs_support = 1, \
2209 .bus_width = DT_INST_PROP(n, bus_width), \
2210 RCAR_MMC_IRQ_CFG_FUNC_INIT(n)}; \
2211 DEVICE_DT_INST_DEFINE(n, rcar_mmc_init, NULL, &mmc_rcar_data_##n, &mmc_rcar_cfg_##n, \
2212 POST_KERNEL, CONFIG_SDHC_INIT_PRIORITY, &rcar_sdhc_api);
2213
2214 DT_INST_FOREACH_STATUS_OKAY(RCAR_MMC_INIT)
2215
