1 /* 2 * Copyright (c) 2023 EPAM Systems 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef __RCAR_MMC_REGISTERS_H__ 7 #define __RCAR_MMC_REGISTERS_H__ 8 9 #include <zephyr/sys/util_macro.h> /* for BIT macro */ 10 11 /* 12 * The command type register is used to select the command type 13 * and response type 14 */ 15 #define RCAR_MMC_CMD 0x000 /* command */ 16 #define RCAR_MMC_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */ 17 #define RCAR_MMC_CMD_MULTI BIT(13) /* multiple block transfer */ 18 #define RCAR_MMC_CMD_RD BIT(12) /* 1: read, 0: write */ 19 #define RCAR_MMC_CMD_DATA BIT(11) /* data transfer */ 20 #define RCAR_MMC_CMD_APP BIT(6) /* ACMD preceded by CMD55 */ 21 #define RCAR_MMC_CMD_NORMAL (0 << 8) /* auto-detect of resp-type */ 22 #define RCAR_MMC_CMD_RSP_NONE (3 << 8) /* response: none */ 23 #define RCAR_MMC_CMD_RSP_R1 (4 << 8) /* response: R1, R5, R6, R7 */ 24 #define RCAR_MMC_CMD_RSP_R1B (5 << 8) /* response: R1b, R5b */ 25 #define RCAR_MMC_CMD_RSP_R2 (6 << 8) /* response: R2 */ 26 #define RCAR_MMC_CMD_RSP_R3 (7 << 8) /* response: R3, R4 */ 27 28 /* Command arguments register for SD card */ 29 #define RCAR_MMC_ARG 0x010 /* command argument */ 30 31 /* 32 * The data stop register is used to enable or disable block counting at 33 * multiple block transfer, and to control the issuing of CMD12 within 34 * command sequences. 35 */ 36 #define RCAR_MMC_STOP 0x020 /* stop action control */ 37 #define RCAR_MMC_STOP_SEC BIT(8) /* use sector count */ 38 #define RCAR_MMC_STOP_STP BIT(0) /* issue CMD12 */ 39 40 /* 41 * The block count register is used to specify the number of 42 * transfer blocks at multiple block transfer. 43 */ 44 #define RCAR_MMC_SECCNT 0x028 /* sector counter */ 45 46 /* The SD card response registers hold the response from the SD card */ 47 #define RCAR_MMC_RSP10 0x030 /* response[39:8] */ 48 #define RCAR_MMC_RSP32 0x040 /* response[71:40] */ 49 #define RCAR_MMC_RSP54 0x050 /* response[103:72] */ 50 #define RCAR_MMC_RSP76 0x060 /* response[127:104] */ 51 52 /* 53 * The SD card interrupt flag register 1 indicates the response end and access 54 * end in the command sequence. This register also indicates the card 55 * detect/write protect state. 56 */ 57 #define RCAR_MMC_INFO1 0x070 /* IRQ status 1 */ 58 #define RCAR_MMC_INFO1_CD BIT(5) /* state of card detect */ 59 #define RCAR_MMC_INFO1_INSERT BIT(4) /* card inserted */ 60 #define RCAR_MMC_INFO1_REMOVE BIT(3) /* card removed */ 61 #define RCAR_MMC_INFO1_CMP BIT(2) /* data complete */ 62 #define RCAR_MMC_INFO1_RSP BIT(0) /* response complete */ 63 64 /* 65 * The SD card interrupt flag register 2 indicates the access status of the 66 * SD buffer and SD card. 67 */ 68 #define RCAR_MMC_INFO2 0x078 /* IRQ status 2 */ 69 #define RCAR_MMC_INFO2_ERR_ILA BIT(15) /* illegal access err */ 70 #define RCAR_MMC_INFO2_CBSY BIT(14) /* command busy */ 71 #define RCAR_MMC_INFO2_SCLKDIVEN BIT(13) /* command setting reg ena */ 72 #define RCAR_MMC_INFO2_CLEAR BIT(11) /* the write value should always be 1 */ 73 #define RCAR_MMC_INFO2_BWE BIT(9) /* write buffer ready */ 74 #define RCAR_MMC_INFO2_BRE BIT(8) /* read buffer ready */ 75 #define RCAR_MMC_INFO2_DAT0 BIT(7) /* SDDAT0 */ 76 #define RCAR_MMC_INFO2_ERR_RTO BIT(6) /* response time out */ 77 #define RCAR_MMC_INFO2_ERR_ILR BIT(5) /* illegal read err */ 78 #define RCAR_MMC_INFO2_ERR_ILW BIT(4) /* illegal write err */ 79 #define RCAR_MMC_INFO2_ERR_TO BIT(3) /* time out error */ 80 #define RCAR_MMC_INFO2_ERR_END BIT(2) /* END bit error */ 81 #define RCAR_MMC_INFO2_ERR_CRC BIT(1) /* CRC error */ 82 #define RCAR_MMC_INFO2_ERR_IDX BIT(0) /* cmd index error */ 83 84 #define RCAR_MMC_INFO2_ERRORS \ 85 (RCAR_MMC_INFO2_ERR_RTO | RCAR_MMC_INFO2_ERR_ILR | \ 86 RCAR_MMC_INFO2_ERR_ILW | RCAR_MMC_INFO2_ERR_TO | \ 87 RCAR_MMC_INFO2_ERR_END | RCAR_MMC_INFO2_ERR_CRC | \ 88 RCAR_MMC_INFO2_ERR_IDX | RCAR_MMC_INFO2_ERR_ILA) 89 90 /* 91 * The interrupt mask 1 register is used to enable or disable 92 * the RCAR_MMC_INFO1 interrupt. 93 */ 94 #define RCAR_MMC_INFO1_MASK 0x080 95 96 /* 97 * The interrupt mask 2 register is used to enable or disable 98 * the RCAR_MMC_INFO2 interrupt. 99 */ 100 #define RCAR_MMC_INFO2_MASK 0x088 101 102 /* 103 * The SD clock control register is used to control 104 * the SD clock output and to set the frequency. 105 */ 106 #define RCAR_MMC_CLKCTL 0x090 107 #define RCAR_MMC_CLKCTL_DIV_MASK 0x104ff 108 #define RCAR_MMC_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */ 109 #define RCAR_MMC_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */ 110 #define RCAR_MMC_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */ 111 #define RCAR_MMC_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */ 112 #define RCAR_MMC_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */ 113 #define RCAR_MMC_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */ 114 #define RCAR_MMC_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */ 115 #define RCAR_MMC_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ 116 #define RCAR_MMC_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ 117 #define RCAR_MMC_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */ 118 #define RCAR_MMC_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ 119 #define RCAR_MMC_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ 120 121 /* 122 * The transfer data length register is used to specify 123 * the transfer data size. 124 */ 125 #define RCAR_MMC_SIZE 0x098 126 127 /* 128 * The SD card access control option register is used to set 129 * the bus width and timeout counter. 130 */ 131 #define RCAR_MMC_OPTION 0x0A0 132 #define RCAR_MMC_OPTION_WIDTH_MASK (5 << 13) 133 #define RCAR_MMC_OPTION_WIDTH_1 (4 << 13) 134 #define RCAR_MMC_OPTION_WIDTH_4 (0 << 13) 135 #define RCAR_MMC_OPTION_WIDTH_8 (1 << 13) 136 137 /* 138 * The SD error status register 1 indicates the CRC status, CRC error, 139 * End error, and CMD error. 140 */ 141 #define RCAR_MMC_ERR_STS1 0x0B0 142 143 /* The SD error status register 2 indicates the timeout state. */ 144 #define RCAR_MMC_ERR_STS2 0x0B8 145 146 /* SD Buffer Read/Write Register */ 147 #define RCAR_MMC_BUF0 0x0C0 148 149 /* The DMA mode enable register enables the DMA transfer. */ 150 #define RCAR_MMC_EXTMODE 0x360 151 #define RCAR_MMC_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */ 152 153 /* The software reset register sets a software reset. */ 154 #define RCAR_MMC_SOFT_RST 0x380 155 #define RCAR_MMC_SOFT_RST_RSTX BIT(0) /* reset deassert */ 156 157 /* The version register indicates the version of the SD host interface. */ 158 #define RCAR_MMC_VERSION 0x388 159 #define RCAR_MMC_VERSION_IP 0xff /* IP version */ 160 161 /* 162 * The host interface mode setting register selects the width for access to 163 * the data bus. 164 */ 165 #define RCAR_MMC_HOST_MODE 0x390 166 167 /* The SD interface mode setting register specifies HS400 mode. */ 168 #define RCAR_MMC_IF_MODE 0x398 169 #define RCAR_MMC_IF_MODE_DDR BIT(0) /* DDR mode */ 170 171 /* Set of DMAC registers */ 172 #define RCAR_MMC_DMA_MODE 0x820 173 #define RCAR_MMC_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */ 174 #define RCAR_MMC_DMA_MODE_WIDTH (BIT(4) | BIT(5)) 175 #define RCAR_MMC_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */ 176 #define RCAR_MMC_DMA_CTL 0x828 177 #define RCAR_MMC_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */ 178 #define RCAR_MMC_DMA_RST 0x830 179 #define RCAR_MMC_DMA_RST_DTRAN0 BIT(8) 180 #define RCAR_MMC_DMA_RST_DTRAN1 BIT(9) 181 #define RCAR_MMC_DMA_INFO1 0x840 182 #define RCAR_MMC_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete (uniphier) */ 183 #define RCAR_MMC_DMA_INFO1_END_RD BIT(17) /* DMA from device is complete (renesas) */ 184 #define RCAR_MMC_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */ 185 #define RCAR_MMC_DMA_INFO1_MASK 0x848 186 #define RCAR_MMC_DMA_INFO2 0x850 187 #define RCAR_MMC_DMA_INFO2_ERR_RD BIT(17) 188 #define RCAR_MMC_DMA_INFO2_ERR_WR BIT(16) 189 #define RCAR_MMC_DMA_INFO2_MASK 0x858 190 #define RCAR_MMC_DMA_ADDR_L 0x880 191 #define RCAR_MMC_DMA_ADDR_H 0x888 192 193 /* set of SCC registers */ 194 195 /* Initial setting register */ 196 #define RENESAS_SDHI_SCC_DTCNTL 0x1000 197 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0) 198 /* Sampling clock position setting register */ 199 #define RENESAS_SDHI_SCC_TAPSET 0x1008 200 #define RENESAS_SDHI_SCC_DT2FF 0x1010 201 /* Sampling Clock Selection Register */ 202 #define RENESAS_SDHI_SCC_CKSEL 0x1018 203 #define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0) 204 /* Sampling Clock Position Correction Register */ 205 #define RENESAS_SDHI_SCC_RVSCNTL 0x1020 206 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 207 /* Sampling Clock Position Correction Request Register */ 208 #define RENESAS_SDHI_SCC_RVSREQ 0x1028 209 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 210 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 211 #define RENESAS_SDHI_SCC_RVSREQ_REQTAP_MASK \ 212 (RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN | RENESAS_SDHI_SCC_RVSREQ_REQTAPUP) 213 #define RENESAS_SDHI_SCC_RVSREQ_ERR BIT(2) 214 /* Sampling data comparison register */ 215 #define RENESAS_SDHI_SCC_SMPCMP 0x1030 216 /* Hardware Adjustment Register 2, used for configuration HS400 mode */ 217 #define RENESAS_SDHI_SCC_TMPPORT2 0x1038 218 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 219 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 220 221 #endif /* __RCAR_MMC_REGISTERS_H__ */ 222
