1# Copyright (c) 2024 Renesas Electronics Corporation
2# SPDX-License-Identifier: Apache-2.0
3
4description: Renesas RA External Bus Clock
5
6compatible: "renesas,ra-cgc-busclk"
7
8include: [clock-controller.yaml, base.yaml]
9
10properties:
11  clk-out-div:
12    type: int
13    enum:
14    - 0
15    - 1
16    - 2
17    description: |
18      Select EBCLK division ratio from BCLK
19      - 0: disable
20      - 1: EBCLK div/1
21      - 2: EBCLK div/2
22
23  sdclk:
24    type: int
25    enum:
26    - 0
27    - 1
28    description: |
29      SDCLK enable or disable
30      - 0: disable
31      - 1: enable
32