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/Zephyr-latest/tests/drivers/counter/counter_basic_api/boards/
Dda1469x_dk_pro.overlay2 clock-src = <&lp_clk>;
3 prescaler = <1>;
8 clock-src = <&divn_clk>;
9 prescaler = <1>;
14 clock-src = <&lp_clk>;
15 prescaler = <2>;
20 clock-src = <&divn_clk>;
21 prescaler = <32>;
/Zephyr-latest/dts/bindings/counter/
Drenesas,smartbond-timer.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,smartbond-timer"
14 clock-src:
20 prescaler:
24 Clock prescaler at the input of the timer
25 Could be in range [0 .. 31] (CLK/(prescaler+1) )
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_mco.c2 * SPDX-License-Identifier: Apache-2.0
24 uint32_t prescaler; member
32 const struct stm32_mco_config *config = dev->config; in stm32_mco_init()
33 const struct stm32_pclken *pclken = &config->pclken[0]; in stm32_mco_init()
36 err = enabled_clock(pclken->bus); in stm32_mco_init()
38 /* Attempt to configure a src clock not available or not valid */ in stm32_mco_init()
44 DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(pclken->enr), in stm32_mco_init()
45 STM32_MCO_CFGR_MASK_GET(pclken->enr) << in stm32_mco_init()
46 STM32_MCO_CFGR_SHIFT_GET(pclken->enr)); in stm32_mco_init()
48 DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(pclken->enr), in stm32_mco_init()
[all …]
Dclock_stm32_ll_wba.c4 * SPDX-License-Identifier: Apache-2.0
19 /* Macros to fill up prescaler values */
38 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler) in get_bus_clock() argument
40 return clock / prescaler; in get_bus_clock()
62 return -ENOTSUP; in enabled_clock()
73 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
75 return -ENOTSUP; in stm32_clock_control_on()
78 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
79 pclken->enr); in stm32_clock_control_on()
81 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
[all …]
Dclock_stm32_ll_common.c2 * Copyright (c) 2017-2022 Linaro Limited.
5 * SPDX-License-Identifier: Apache-2.0
22 /* Macros to fill up prescaler values */
76 #define RCC_PLLP_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)
81 #define RCC_PLLQ_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)
100 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler) in get_bus_clock() argument
102 return clock / prescaler; in get_bus_clock()
136 r = -ENOTSUP; in enabled_clock()
150 r = -ENOTSUP; in enabled_clock()
157 r = -ENOTSUP; in enabled_clock()
[all …]
Dclock_stm32_ll_u5.c6 * SPDX-License-Identifier: Apache-2.0
22 /* Macros to fill up prescaler values */
39 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler) in get_bus_clock() argument
41 return clock / prescaler; in get_bus_clock()
150 return -ENOTSUP; in enabled_clock()
161 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
163 return -ENOTSUP; in stm32_clock_control_on()
166 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
167 pclken->enr); in stm32_clock_control_on()
169 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
[all …]
Dclock_stm32_ll_h7.c7 * SPDX-License-Identifier: Apache-2.0
22 /* Macros to fill up prescaler values */
56 /* Choose PLL SRC */
78 /* SYSCLKSRC before the D1CPRE prescaler */
89 /* ARM Sys CPU Clock before HPRE prescaler */
169 * D1CPRE prescaler allows to set a HCLK frequency lower than SYSCLK frequency.
171 * So, changing this prescaler is not allowed until it is made possible to
174 #error "D1CPRE prescaler can't be higher than 1"
186 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler) in get_bus_clock() argument
188 return clock / prescaler; in get_bus_clock()
[all …]
/Zephyr-latest/samples/drivers/counter/alarm/boards/
Dda1469x_dk_pro.overlay2 clock-src = <&lp_clk>;
3 prescaler = <1>;
/Zephyr-latest/boards/infineon/xmc47_relax_kit/
Dxmc47_relax_kit.dts2 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
11 #include <infineon/cat3/xmc/xmc4700_F144x2048-intc.dtsi>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include "xmc47_relax_kit-pinctrl.dtsi"
22 die-temp0 = &die_temp;
23 pwm-led0 = &pwm_led1;
29 compatible = "gpio-leds";
40 compatible = "pwm-leds";
55 zephyr,shell-uart = &usic0ch0;
[all …]
/Zephyr-latest/drivers/can/
Dcan_mcux_flexcan.c4 * SPDX-License-Identifier: Apache-2.0
47 #define MCUX_FLEXCAN_MAX_TX (MCUX_FLEXCAN_MAX_MB - MCUX_FLEXCAN_MAX_RX)
60 #define TX_MBIDX_TO_ALLOC_IDX(x) (x - MCUX_FLEXCAN_MAX_RX)
124 const struct mcux_flexcan_config *config = dev->config; in mcux_flexcan_get_core_clock()
126 return clock_control_get_rate(config->clock_dev, config->clock_subsys, rate); in mcux_flexcan_get_core_clock()
139 struct mcux_flexcan_data *data = dev->data; in mcux_flexcan_set_timing()
142 return -EINVAL; in mcux_flexcan_set_timing()
145 if (data->common.started) { in mcux_flexcan_set_timing()
146 return -EBUSY; in mcux_flexcan_set_timing()
149 data->timing = *timing; in mcux_flexcan_set_timing()
[all …]
Dcan_mcp251xfd.c5 * SPDX-License-Identifier: Apache-2.0
22 static void mcp251xfd_canframe_to_txobj(const struct can_frame *src, int mailbox_idx, in mcp251xfd_canframe_to_txobj() argument
27 if ((src->flags & CAN_FRAME_IDE) != 0) { in mcp251xfd_canframe_to_txobj()
28 dst->id = FIELD_PREP(MCP251XFD_OBJ_ID_SID_MASK, src->id >> 18); in mcp251xfd_canframe_to_txobj()
29 dst->id |= FIELD_PREP(MCP251XFD_OBJ_ID_EID_MASK, src->id); in mcp251xfd_canframe_to_txobj()
31 dst->flags |= MCP251XFD_OBJ_FLAGS_IDE; in mcp251xfd_canframe_to_txobj()
33 dst->id = FIELD_PREP(MCP251XFD_OBJ_ID_SID_MASK, src->id); in mcp251xfd_canframe_to_txobj()
36 if ((src->flags & CAN_FRAME_BRS) != 0) { in mcp251xfd_canframe_to_txobj()
37 dst->flags |= MCP251XFD_OBJ_FLAGS_BRS; in mcp251xfd_canframe_to_txobj()
40 dst->flags |= FIELD_PREP(MCP251XFD_OBJ_FLAGS_DLC_MASK, src->dlc); in mcp251xfd_canframe_to_txobj()
[all …]
Dcan_mcux_mcan.c4 * SPDX-License-Identifier: Apache-2.0
36 const struct can_mcan_config *mcan_config = dev->config; in mcux_mcan_read_reg()
37 const struct mcux_mcan_config *mcux_config = mcan_config->custom; in mcux_mcan_read_reg()
39 return can_mcan_sys_read_reg(mcux_config->base, reg, val); in mcux_mcan_read_reg()
44 const struct can_mcan_config *mcan_config = dev->config; in mcux_mcan_write_reg()
45 const struct mcux_mcan_config *mcux_config = mcan_config->custom; in mcux_mcan_write_reg()
47 return can_mcan_sys_write_reg(mcux_config->base, reg, val); in mcux_mcan_write_reg()
52 const struct can_mcan_config *mcan_config = dev->config; in mcux_mcan_read_mram()
53 const struct mcux_mcan_config *mcux_config = mcan_config->custom; in mcux_mcan_read_mram()
55 return can_mcan_sys_read_mram(mcux_config->mram, offset, dst, len); in mcux_mcan_read_mram()
[all …]
Dcan_stm32h7_fdcan.c5 * SPDX-License-Identifier: Apache-2.0
46 const struct can_mcan_config *mcan_cfg = dev->config; in can_stm32h7_read_reg()
47 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom; in can_stm32h7_read_reg()
49 return can_mcan_sys_read_reg(stm32h7_cfg->base, reg, val); in can_stm32h7_read_reg()
54 const struct can_mcan_config *mcan_cfg = dev->config; in can_stm32h7_write_reg()
55 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom; in can_stm32h7_write_reg()
57 return can_mcan_sys_write_reg(stm32h7_cfg->base, reg, val); in can_stm32h7_write_reg()
62 const struct can_mcan_config *mcan_cfg = dev->config; in can_stm32h7_read_mram()
63 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom; in can_stm32h7_read_mram()
65 return can_mcan_sys_read_mram(stm32h7_cfg->mram, offset, dst, len); in can_stm32h7_read_mram()
[all …]
/Zephyr-latest/dts/bindings/pwm/
Dnxp,s32-emios-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
11 - Channel 0 for mode OPWFMB
12 - Channel 1 for mode OPWMB
13 - Channel 2 for mode OPWMCB with deadtime inserted at leading edge
14 - Channel 3 for mode SAIC, use internal timebase with input filter = 2 eMIOS clock
19 pwm-mode = "OPWFMB";
20 prescaler = <8>;
22 duty-cycle = <32768>;
28 master-bus = <&emios1_bus_a>;
29 pwm-mode = "OPWMB";
[all …]
/Zephyr-latest/dts/arm/renesas/smartbond/
Dda1469x.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/adc/smartbond-adc.h>
11 #include <zephyr/dt-bindings/pinctrl/smartbond-pinctrl.h>
12 #include <zephyr/dt-bindings/dma/dma_smartbond.h>
17 zephyr,flash-controller = &flash_controller;
21 compatible = "zephyr,lvgl-pointer-input";
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/Zephyr-latest/drivers/pwm/
Dpwm_nxp_s32_emios.c4 * SPDX-License-Identifier: Apache-2.0
94 return -EINVAL; in pwm_nxp_s32_set_cycles_internal_timebase()
106 return -EIO; in pwm_nxp_s32_set_cycles_internal_timebase()
128 return -EINVAL; in pwm_nxp_s32_set_cycles_external_timebase()
140 return -EIO; in pwm_nxp_s32_set_cycles_external_timebase()
147 return -EIO; in pwm_nxp_s32_set_cycles_external_timebase()
159 const struct pwm_nxp_s32_config *config = dev->config; in pwm_nxp_s32_set_cycles()
160 struct pwm_nxp_s32_data *data = dev->data; in pwm_nxp_s32_set_cycles()
167 return -EINVAL; in pwm_nxp_s32_set_cycles()
170 if (eMios_Pwm_Ip_IndexInChState[config->instance][channel] >= in pwm_nxp_s32_set_cycles()
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_rt10xx.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/imx_ccm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
19 die-temp0 = &tempmon;
23 #address-cells = <1>;
[all …]
Dnxp_rt11xx.dtsi2 * Copyright 2021,2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/power/imx_spc.h>
15 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
[all …]
Dnxp_rt1010.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 flexram,num-ram-banks = <4>;
12 flexram,bank-spec = <FLEXRAM_OCRAM>,
19 clock-frequency = <500000000>;
35 /delete-node/ arm-podf;
37 ipg-podf {
38 clock-div = <4>;
61 irq-shared-offset = <0>;
62 dma-channels = <16>;
67 /* Remove GPIO3-GPIO9, they don't exist on RT1010 */
[all …]
Dnxp_mcxn23x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <arm/armv8-m.dtsi>
12 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-m33f";
22 #address-cells = <1>;
[all …]
Dnxp_mcxn94x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <arm/armv8-m.dtsi>
12 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-m33f";
22 #address-cells = <1>;
[all …]
/Zephyr-latest/boards/infineon/xmc45_relax_kit/
Dxmc45_relax_kit.dts2 * SPDX-License-Identifier: Apache-2.0
9 /dts-v1/;
12 #include <infineon/cat3/xmc/xmc4500_F100x1024-intc.dtsi>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include "xmc45_relax_kit-pinctrl.dtsi"
18 compatible = "infineon,xm4500-relax-kit", "infineon,xmc4500",
23 die-temp0 = &die_temp;
24 pwm-led0 = &pwm_led1;
30 compatible = "gpio-leds";
41 compatible = "pwm-leds";
[all …]
/Zephyr-latest/drivers/led/
Dlp5562.c4 * SPDX-License-Identifier: Apache-2.0
13 * The LP5562 is a 4-channel LED driver that communicates over I2C. The four
23 * - Set the brightness.
24 * - Fade the brightness over time.
25 * - Loop parts of the program or the whole program.
26 * - Add delays.
27 * - Synchronize between the engines.
70 * 15.6ms per step if the prescaler is set to 1. We round the step length
77 * The minimum waiting period is 0.49ms with the prescaler set to 0 and one
189 * @retval -EINVAL If an invalid channel is given.
[all …]
/Zephyr-latest/dts/arm/microchip/
Dmec1501hsz.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4";
[all …]
/Zephyr-latest/doc/releases/
Drelease-notes-1.9.rst29 * STM32 PWM prescaler issue fixed
49 * Bluetooth Qualification-ready BLE Controller
82 * ARC: Nested interrupt support for normal, non-FIRQ interrupts
90 * arm: Added Olimex STM32-E407 and STM32-P405 boards
91 * arm: Added STM32F412 Nucleo and STM32F429I-DISC1 boards
116 * net-app API support added. This is higher level API that can be used
126 networking applications using a well-known, cross-platform API
140 * IPSP net-app support: a simplified networking API reducing duplication
143 * BLE controller qualification-ready, with all required tests passing
144 * Controller-based privacy (including all optional features)
[all …]

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