2  * Copyright (c) 2017-2022 Linaro Limited.
5  * SPDX-License-Identifier: Apache-2.0
22 /* Macros to fill up prescaler values */
76 #define RCC_PLLP_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)
81 #define RCC_PLLQ_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)
100 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)  in get_bus_clock()  argument
102 	return clock / prescaler;  in get_bus_clock()
136 			r = -ENOTSUP;  in enabled_clock()
150 			r = -ENOTSUP;  in enabled_clock()
157 			r = -ENOTSUP;  in enabled_clock()
164 			r = -ENOTSUP;  in enabled_clock()
171 			r = -ENOTSUP;  in enabled_clock()
178 			r = -ENOTSUP;  in enabled_clock()
185 			r = -ENOTSUP;  in enabled_clock()
192 			r = -ENOTSUP;  in enabled_clock()
199 			r = -ENOTSUP;  in enabled_clock()
206 			r = -ENOTSUP;  in enabled_clock()
213 			r = -ENOTSUP;  in enabled_clock()
220 			r = -ENOTSUP;  in enabled_clock()
227 			r = -ENOTSUP;  in enabled_clock()
234 			r = -ENOTSUP;  in enabled_clock()
241 			r = -ENOTSUP;  in enabled_clock()
246 		return -ENOTSUP;  in enabled_clock()
260 	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {  in stm32_clock_control_on()
262 		return -ENOTSUP;  in stm32_clock_control_on()
265 	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,  in stm32_clock_control_on()
266 		     pclken->enr);  in stm32_clock_control_on()
270 	temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);  in stm32_clock_control_on()
283 	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {  in stm32_clock_control_off()
285 		return -ENOTSUP;  in stm32_clock_control_off()
288 	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,  in stm32_clock_control_off()
289 		       pclken->enr);  in stm32_clock_control_off()
299 	/* At least one alt src clock available */  in stm32_clock_control_configure()
306 	err = enabled_clock(pclken->bus);  in stm32_clock_control_configure()
308 		/* Attempt to configure a src clock not available or not valid */  in stm32_clock_control_configure()
312 	if (pclken->enr == NO_SEL) {  in stm32_clock_control_configure()
317 	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),  in stm32_clock_control_configure()
318 		       STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));  in stm32_clock_control_configure()
319 	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),  in stm32_clock_control_configure()
320 		     STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));  in stm32_clock_control_configure()
324 	/* No src clock available: Not supported */  in stm32_clock_control_configure()
325 	return -ENOTSUP;  in stm32_clock_control_configure()
335 	 * Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)  in stm32_clock_control_get_subsys_rate()
345 	/* APB2 bus exists, but w/o dedicated prescaler */  in stm32_clock_control_get_subsys_rate()
352 	/* AHB3 bus exists, but w/o dedicated prescaler */  in stm32_clock_control_get_subsys_rate()
357 	if (pclken->bus == STM32_SRC_PCLK) {  in stm32_clock_control_get_subsys_rate()
360 		return -ENOTSUP;  in stm32_clock_control_get_subsys_rate()
366 	switch (pclken->bus) {  in stm32_clock_control_get_subsys_rate()
394 		/* STM32WL: AHB3 and APB3 share the same clock and prescaler. */  in stm32_clock_control_get_subsys_rate()
406 			return -EIO;  in stm32_clock_control_get_subsys_rate()
491 		return -ENOTSUP;  in stm32_clock_control_get_subsys_rate()
494 	if (pclken->div) {  in stm32_clock_control_get_subsys_rate()
495 		*rate /= (pclken->div + 1);  in stm32_clock_control_get_subsys_rate()
508 	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == true) {  in stm32_clock_control_get_status()
510 		if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)  in stm32_clock_control_get_status()
511 		    == pclken->enr) {  in stm32_clock_control_get_status()
518 		if (enabled_clock(pclken->bus) == 0) {  in stm32_clock_control_get_status()
561 	 * Case of chain-loaded applications:  in set_up_plls()
603 	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, pllp(STM32_PLL_P_DIVISOR));  in set_up_plls()
607 	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, pllq(STM32_PLL_Q_DIVISOR));  in set_up_plls()
720 		/* LSE belongs to the back-up domain, enable access.*/  in set_up_fixed_clock_sources()
786 		 * No-op on other series.  in set_up_fixed_clock_sources()
881 	/* Set bus prescalers prescaler */  in stm32_clock_control_init()