1/*
2 * SPDX-License-Identifier: Apache-2.0
3 *
4 * Copyright (c) 2020 Linumiz
5 * Author: Parthiban Nallathambi <parthiban@linumiz.com>
6 *
7 */
8
9/dts-v1/;
10
11#include <infineon/cat3/xmc/xmc4500_F100x1024.dtsi>
12#include <infineon/cat3/xmc/xmc4500_F100x1024-intc.dtsi>
13#include <zephyr/dt-bindings/pwm/pwm.h>
14#include "xmc45_relax_kit-pinctrl.dtsi"
15
16/ {
17	model = "Infineon XMC4500 Relax Kit";
18	compatible = "infineon,xm4500-relax-kit", "infineon,xmc4500",
19						"infineon,xmc4xxx";
20
21	aliases {
22		led0 = &led1;
23		die-temp0 = &die_temp;
24		pwm-led0 = &pwm_led1;
25		watchdog0 = &wdt0;
26		rtc = &rtc;
27	};
28
29	leds {
30		compatible = "gpio-leds";
31		/* leds are labelled LED1 and LED2 in the relax kit documentation */
32		led1: led1 {
33			gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
34		};
35		led2: led2 {
36			gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
37		};
38	};
39
40	pwmleds {
41		compatible = "pwm-leds";
42		pwm_led1: pwm_led1 {
43			pwms = <&pwm_ccu40 2 PWM_SEC(1) PWM_POLARITY_NORMAL>;
44			label = "PWM LED1";
45		};
46		pwm_led2: pwm_led2 {
47			pwms = <&pwm_ccu40 3 PWM_SEC(1) PWM_POLARITY_NORMAL>;
48			label = "PWM LED2";
49		};
50	};
51
52	chosen {
53		zephyr,sram = &dsram1;
54		zephyr,flash = &flash0;
55		zephyr,console = &usic1ch1;
56		zephyr,shell-uart = &usic1ch1;
57		zephyr,flash-controller = &flash_controller;
58		zephyr,code-partition = &code_partition;
59	};
60};
61
62&psram1 {
63	compatible = "zephyr,memory-region", "mmio-sram";
64	zephyr,memory-region = "PSRAM1";
65};
66
67&dsram2 {
68	compatible = "zephyr,memory-region", "mmio-sram";
69	zephyr,memory-region = "DSRAM2";
70};
71
72&flash_controller {
73	status = "okay";
74};
75
76&flash0 {
77	partitions {
78		compatible = "fixed-partitions";
79		#address-cells = <1>;
80		#size-cells = <1>;
81
82		code_partition: partition@0 {
83			reg = <0x0 0x80000>;
84			read-only;
85		};
86
87		storage_partition: partition@80000 {
88			label = "storage";
89			reg = <0x80000 0x80000>;
90		};
91	};
92};
93
94&cpu0 {
95	clock-frequency = <120000000>;
96};
97
98&usic1ch1 {
99	compatible = "infineon,xmc4xxx-uart";
100	current-speed = <115200>;
101	pinctrl-0 = <&uart_tx_p0_1_u1c1 &uart_rx_p0_0_u1c1>;
102	pinctrl-names = "default";
103	input-src = "DX0D";
104	interrupts = <90 1 91 1>;
105	interrupt-names = "tx", "rx";
106	fifo-start-offset = <0>;
107	fifo-tx-size = <16>;
108	fifo-rx-size = <16>;
109	status = "okay";
110};
111
112&adc0 {
113	vref-internal-mv = <3300>;
114};
115
116&adc1 {
117	vref-internal-mv = <3300>;
118};
119
120&adc2 {
121	vref-internal-mv = <3300>;
122};
123
124&adc3 {
125	vref-internal-mv = <3300>;
126};
127
128&gpio1 {
129	status = "okay";
130};
131
132&pwm_ccu40 {
133	slice-prescaler = <15 15 15 15>;
134	pinctrl-0 = <&pwm_out_p1_0_ccu40_ch3 &pwm_out_p1_1_ccu40_ch2>;
135	pinctrl-names = "default";
136};
137
138&eth {
139	status = "okay";
140	pinctrl-0 = <&eth_p2_4_rxer &eth_p2_2_rxd0 &eth_p2_3_rxd1
141		     &eth_p15_8_clk_rmii &eth_p15_9_crs_dv &eth_p2_5_tx_en
142		     &eth_p2_8_txd0 &eth_p2_9_txd1>;
143	pinctrl-names = "default";
144
145	rxer-port-ctrl = "P2_4";
146	rxd0-port-ctrl = "P2_2";
147	rxd1-port-ctrl = "P2_3";
148	rmii-rx-clk-port-ctrl = "P15_8";
149	crs-rx-dv-port-ctrl = "P15_9";
150
151	phy-connection-type = "rmii";
152	phy-handle = <&phy>;
153};
154
155&mdio {
156	status = "okay";
157	mdi-port-ctrl = "P2_0";
158	pinctrl-0 = <&eth_p2_0_mdo &eth_p2_7_mdc>;
159	pinctrl-names = "default";
160
161	phy: ethernet-phy@0 {
162		compatible = "ethernet-phy";
163		reg = <0>;
164	};
165};
166
167&rtc {
168	status = "okay";
169};
170