5  * SPDX-License-Identifier: Apache-2.0
46 	const struct can_mcan_config *mcan_cfg = dev->config;  in can_stm32h7_read_reg()
47 	const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;  in can_stm32h7_read_reg()
49 	return can_mcan_sys_read_reg(stm32h7_cfg->base, reg, val);  in can_stm32h7_read_reg()
54 	const struct can_mcan_config *mcan_cfg = dev->config;  in can_stm32h7_write_reg()
55 	const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;  in can_stm32h7_write_reg()
57 	return can_mcan_sys_write_reg(stm32h7_cfg->base, reg, val);  in can_stm32h7_write_reg()
62 	const struct can_mcan_config *mcan_cfg = dev->config;  in can_stm32h7_read_mram()
63 	const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;  in can_stm32h7_read_mram()
65 	return can_mcan_sys_read_mram(stm32h7_cfg->mram, offset, dst, len);  in can_stm32h7_read_mram()
68 static int can_stm32h7_write_mram(const struct device *dev, uint16_t offset, const void *src,  in can_stm32h7_write_mram()  argument
71 	const struct can_mcan_config *mcan_cfg = dev->config;  in can_stm32h7_write_mram()
72 	const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;  in can_stm32h7_write_mram()
74 	return can_mcan_sys_write_mram(stm32h7_cfg->mram, offset, src, len);  in can_stm32h7_write_mram()
79 	const struct can_mcan_config *mcan_cfg = dev->config;  in can_stm32h7_clear_mram()
80 	const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;  in can_stm32h7_clear_mram()
82 	return can_mcan_sys_clear_mram(stm32h7_cfg->mram, offset, len);  in can_stm32h7_clear_mram()
94 		return -EIO;  in can_stm32h7_get_core_clock()
97 	cdiv = FIELD_GET(FDCANCCU_CCFG_CDIV, FDCAN_CCU->CCFG);  in can_stm32h7_get_core_clock()
109 	const struct can_mcan_config *mcan_cfg = dev->config;  in can_stm32h7_clock_enable()
110 	const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;  in can_stm32h7_clock_enable()
117 		return -ENODEV;  in can_stm32h7_clock_enable()
120 	if (IS_ENABLED(STM32H7_FDCAN_DOMAIN_CLOCK_SUPPORT) && (stm32h7_cfg->pclk_len > 1)) {  in can_stm32h7_clock_enable()
122 				(clock_control_subsys_t)&stm32h7_cfg->pclken[1],  in can_stm32h7_clock_enable()
135 			(clock_control_subsys_t)&stm32h7_cfg->pclken[1], &fdcan_clock);  in can_stm32h7_clock_enable()
144 			return -ENODEV;  in can_stm32h7_clock_enable()
148 	ret = clock_control_on(clk, (clock_control_subsys_t)&stm32h7_cfg->pclken[0]);  in can_stm32h7_clock_enable()
154 	if (stm32h7_cfg->clock_divider != 0U) {  in can_stm32h7_clock_enable()
157 		FDCAN_CCU->CCFG = FDCANCCU_CCFG_BCC |  in can_stm32h7_clock_enable()
158 			FIELD_PREP(FDCANCCU_CCFG_CDIV, stm32h7_cfg->clock_divider >> 1U);  in can_stm32h7_clock_enable()
166 	const struct can_mcan_config *mcan_cfg = dev->config;  in can_stm32h7_init()
167 	const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;  in can_stm32h7_init()
171 	ret = pinctrl_apply_state(stm32h7_cfg->pcfg, PINCTRL_STATE_DEFAULT);  in can_stm32h7_init()
182 	ret = can_mcan_configure_mram(dev, stm32h7_cfg->mrba, stm32h7_cfg->mram);  in can_stm32h7_init()
192 	stm32h7_cfg->config_irq();  in can_stm32h7_init()
214 	 * section 56.5.7, FDCAN nominal bit timing and prescaler register
225 	 * (RM0433 Rev 7), section 56.5.3, FDCAN data bit timing and prescaler