6  * SPDX-License-Identifier: Apache-2.0
22 /* Macros to fill up prescaler values */
39 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)  in get_bus_clock()  argument
41 	return clock / prescaler;  in get_bus_clock()
150 	return -ENOTSUP;  in enabled_clock()
161 	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {  in stm32_clock_control_on()
163 		return -ENOTSUP;  in stm32_clock_control_on()
166 	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,  in stm32_clock_control_on()
167 		     pclken->enr);  in stm32_clock_control_on()
169 	temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);  in stm32_clock_control_on()
182 	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {  in stm32_clock_control_off()
184 		return -ENOTSUP;  in stm32_clock_control_off()
187 	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,  in stm32_clock_control_off()
188 		       pclken->enr);  in stm32_clock_control_off()
203 	err = enabled_clock(pclken->bus);  in stm32_clock_control_configure()
205 		/* Attempt to configure a src clock not available or not valid */  in stm32_clock_control_configure()
209 	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),  in stm32_clock_control_configure()
210 		       STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));  in stm32_clock_control_configure()
211 	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),  in stm32_clock_control_configure()
212 		     STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));  in stm32_clock_control_configure()
224 	 * Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)  in stm32_clock_control_get_subsys_rate()
236 	switch (pclken->bus) {  in stm32_clock_control_get_subsys_rate()
357 		return -ENOTSUP;  in stm32_clock_control_get_subsys_rate()
360 	if (pclken->div) {  in stm32_clock_control_get_subsys_rate()
361 		*rate /= (pclken->div + 1);  in stm32_clock_control_get_subsys_rate()
374 	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == true) {  in stm32_clock_control_get_status()
376 		if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)  in stm32_clock_control_get_status()
377 		    == pclken->enr) {  in stm32_clock_control_get_status()
384 		if (enabled_clock(pclken->bus) == 0) {  in stm32_clock_control_get_status()
412 		return -ERANGE;  in get_vco_input_range()
437  * The goal of this function is to set the epod prescaler, so that epod clock freq
439  * Up to now only MSI as PLL1 source clock can be > 16MHz, requiring a epod prescaler > 1
440  * For HSI16, epod prescaler is default (div1, not divided).
441  * Once HSE is > 16MHz, the epod prescaler would also be also required.
445 	/* Reset Epod Prescaler in case it was set earlier with another DIV value */  in set_epod_booster()
454 		 * Set EPOD clock prescaler based on PLL1 input freq  in set_epod_booster()
542 		return -ENOTSUP;  in set_up_plls()
604 		return -ENOTSUP;  in set_up_plls()
626 		SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN);  in set_up_plls()
631 		SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN);  in set_up_plls()
636 		SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN);  in set_up_plls()
656 		return -ENOTSUP;  in set_up_plls()
678 		SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN);  in set_up_plls()
683 		SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN);  in set_up_plls()
688 		SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN);  in set_up_plls()
899 		return -ENOTSUP;  in stm32_clock_control_init()