Lines Matching +full:prescaler +full:- +full:src
7 * SPDX-License-Identifier: Apache-2.0
22 /* Macros to fill up prescaler values */
56 /* Choose PLL SRC */
78 /* SYSCLKSRC before the D1CPRE prescaler */
89 /* ARM Sys CPU Clock before HPRE prescaler */
169 * D1CPRE prescaler allows to set a HCLK frequency lower than SYSCLK frequency.
171 * So, changing this prescaler is not allowed until it is made possible to
174 #error "D1CPRE prescaler can't be higher than 1"
186 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler) in get_bus_clock() argument
188 return clock / prescaler; in get_bus_clock()
339 return -ERANGE;
381 return -ENOTSUP;
392 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
394 return -ENOTSUP;
399 sys_set_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr);
403 temp = sys_read32(STM32H7_BUS_CLK_REG + pclken->bus);
418 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
420 return -ENOTSUP;
425 sys_clear_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr);
442 err = enabled_clock(pclken->bus);
444 /* Attempt to configure a src clock not available or not valid */
450 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
451 STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
452 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
453 STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
466 * Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
490 switch (pclken->bus) {
579 /* PLL 1 has no T-divider */
642 /* PLL 3 has no T-divider */
646 return -ENOTSUP;
649 if (pclken->div) {
650 *rate /= (pclken->div + 1);
772 * Case of chain-loaded applications:
827 return -ENOTSUP;
998 switch (RCC->CFGR & RCC_CFGR_SWS) {
1000 sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)
1017 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
1018 pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos);
1020 if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) != 0U) {
1021 pllfracn = (float_t)(uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN)
1031 ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) +
1037 ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) +
1043 hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >>
1046 ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) +
1051 pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >>
1060 sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos));
1065 core_presc = (RCC->CDCFGR & RCC_CDCFGR_CPRE);
1068 SystemCoreClock = (sysclk >> (core_presc - RCC_CDCFGR_CPRE_3 + 1U));
1167 return -ENOTSUP;