1/*
2 * Copyright (c) 2019 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <zephyr/dt-bindings/adc/adc.h>
9#include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
13
14/ {
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu0: cpu@0 {
20			device_type = "cpu";
21			compatible = "arm,cortex-m4";
22			reg = <0>;
23			cpu-power-states = <&idle &suspend_to_ram>;
24		};
25
26		power-states {
27			idle: idle {
28				compatible = "zephyr,power-state";
29				power-state-name = "suspend-to-idle";
30				min-residency-us = <1000000>;
31			};
32
33			suspend_to_ram: suspend_to_ram {
34				compatible = "zephyr,power-state";
35				power-state-name = "suspend-to-ram";
36				min-residency-us = <2000000>;
37			};
38		};
39	};
40
41	flash0: flash@e0000 {
42		reg = <0x000E0000 0x38000>;
43	};
44
45	sram0: memory@118000 {
46		compatible = "mmio-sram";
47		reg = <0x00118000 0x8000>;
48	};
49
50	aliases {
51		i2c-smb-0 = &i2c_smb_0;
52		i2c-smb-1 = &i2c_smb_1;
53		i2c-smb-2 = &i2c_smb_2;
54		i2c-smb-3 = &i2c_smb_3;
55		i2c-smb-4 = &i2c_smb_4;
56	};
57
58	soc {
59		ecs: ecs@4000fc00 {
60			compatible = "microchip,xec-ecs";
61			reg = <0x4000fc00 0x200>;
62		};
63		pcr: pcr@40080100 {
64			compatible = "microchip,xec-pcr";
65			reg = <0x40080100 0x100 0x4000a400 0x100>;
66			reg-names = "pcrr", "vbatr";
67			core-clock-div = <1>;
68			/* MEC15xx requires both sources to be the same */
69			pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
70			periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
71			clk32kmon-period-min = <1435>;
72			clk32kmon-period-max = <1495>;
73			clk32kmon-duty-cycle-var-max = <132>;
74			clk32kmon-valid-min = <4>;
75			xtal-enable-delay-ms = <300>;
76			pll-lock-timeout-ms = <30>;
77			#clock-cells = <3>;
78		};
79		ecia: ecia@4000e000 {
80			reg = <0x4000e000 0x400>;
81			#address-cells = <1>;
82			#size-cells = <1>;
83
84			girq23: girq23@12c {
85				reg = <0x12c 0x14>;
86				interrupts = <14 0>;
87				girq-id = <15>;
88				sources = <0 1 2 4 5 10 16 17>;
89				status = "disabled";
90			};
91		};
92		pinctrl: pin-controller@40081000 {
93			compatible = "microchip,xec-pinctrl";
94			#address-cells = <1>;
95			#size-cells = <1>;
96			reg = <0x40081000 0x1000>;
97
98			gpio_000_036: gpio@40081000 {
99				compatible = "microchip,xec-gpio";
100				reg = < 0x40081000 0x80 0x40081300 0x04
101					0x40081380 0x04 0x400813fc 0x04>;
102				interrupts = <3 2>;
103				gpio-controller;
104				port-id = <0>;
105				girq-id = <11>;
106				#gpio-cells=<2>;
107			};
108			gpio_040_076: gpio@40081080 {
109				compatible = "microchip,xec-gpio";
110				reg = < 0x40081080 0x80 0x40081304 0x04
111					0x40081384 0x04 0x400813f8 0x4>;
112				interrupts = <2 2>;
113				gpio-controller;
114				port-id = <1>;
115				girq-id = <10>;
116				#gpio-cells=<2>;
117			};
118			gpio_100_136: gpio@40081100 {
119				compatible = "microchip,xec-gpio";
120				reg = < 0x40081100 0x80 0x40081308 0x04
121					0x40081388 0x04 0x400813f4 0x04>;
122				gpio-controller;
123				interrupts = <1 2>;
124				port-id = <2>;
125				girq-id = <9>;
126				#gpio-cells=<2>;
127			};
128			gpio_140_176: gpio@40081180 {
129				compatible = "microchip,xec-gpio";
130				reg = < 0x40081180 0x80 0x4008130c 0x04
131					0x4008138c 0x04 0x400813f0 0x04>;
132				gpio-controller;
133				interrupts = <0 2>;
134				port-id = <3>;
135				girq-id = <8>;
136				#gpio-cells=<2>;
137			};
138			gpio_200_236: gpio@40081200 {
139				compatible = "microchip,xec-gpio";
140				reg = < 0x40081200 0x80 0x40081310 0x04
141					0x40081390 0x04 0x400813ec 0x04>;
142				gpio-controller;
143				interrupts = <4 2>;
144				port-id = <4>;
145				girq-id = <12>;
146				#gpio-cells=<2>;
147			};
148			gpio_240_276: gpio@40081280 {
149				compatible = "microchip,xec-gpio";
150				reg = < 0x40081280 0x80 0x40081314 0x04
151					0x40081394 0x04 0x400813e8 0x04>;
152				gpio-controller;
153				interrupts = <17 2>;
154				port-id = <5>;
155				girq-id = <26>;
156				#gpio-cells=<2>;
157			};
158		};
159		rtimer: timer@40007400 {
160			compatible = "microchip,xec-rtos-timer";
161			reg = <0x40007400 0x10>;
162			interrupts = <111 0>;
163			girqs = <23 10>;
164		};
165		bbram: bb-ram@4000a800 {
166			compatible = "microchip,xec-bbram";
167			reg = <0x4000a800 0x80>;
168			reg-names = "memory";
169		};
170		wdog: watchdog@40000400 {
171			compatible = "microchip,xec-watchdog";
172			reg = <0x40000400 0x400>;
173			interrupts = <171 0>;
174			girqs = <21 2>;
175			pcrs = <1 9>;
176		};
177		uart0: uart@400f2400 {
178			compatible = "microchip,xec-uart";
179			reg = <0x400f2400 0x400>;
180			interrupts = <40 0>;
181			clock-frequency = <1843200>;
182			current-speed = <38400>;
183			girqs = <15 0>;
184			pcrs = <2 1>;
185			ldn = <9>;
186			status = "disabled";
187		};
188		uart1: uart@400f2800 {
189			compatible = "microchip,xec-uart";
190			reg = <0x400f2800 0x400>;
191			interrupts = <41 0>;
192			clock-frequency = <1843200>;
193			current-speed = <38400>;
194			girqs = <15 1>;
195			pcrs = <2 2>;
196			ldn = <10>;
197			status = "disabled";
198		};
199		uart2: uart@400f2c00 {
200			compatible = "microchip,xec-uart";
201			reg = <0x400f2c00 0x400>;
202			interrupts = <44 0>;
203			clock-frequency = <1843200>;
204			current-speed = <38400>;
205			girqs = <15 4>;
206			pcrs = <2 28>;
207			ldn = <11>;
208			status = "disabled";
209		};
210
211		i2c_smb_0: i2c@40004000 {
212			compatible = "microchip,xec-i2c";
213			reg = <0x40004000 0x80>;
214			clock-frequency = <I2C_BITRATE_STANDARD>;
215			interrupts = <20 1>;
216			pcrs = <1 10>;
217			#address-cells = <1>;
218			#size-cells = <0>;
219			status = "disabled";
220			girq = <13>;
221			girq-bit = <0>;
222		};
223
224		i2c_smb_1: i2c@40004400 {
225			compatible = "microchip,xec-i2c";
226			reg = <0x40004400 0x80>;
227			clock-frequency = <I2C_BITRATE_STANDARD>;
228			interrupts = <21 1>;
229			pcrs = <3 13>;
230			#address-cells = <1>;
231			#size-cells = <0>;
232			status = "disabled";
233			girq = <13>;
234			girq-bit = <1>;
235		};
236
237		i2c_smb_2: i2c@40004800 {
238			compatible = "microchip,xec-i2c";
239			reg = <0x40004800 0x80>;
240			clock-frequency = <I2C_BITRATE_STANDARD>;
241			interrupts = <22 1>;
242			pcrs = <3 14>;
243			#address-cells = <1>;
244			#size-cells = <0>;
245			status = "disabled";
246			girq = <13>;
247			girq-bit = <2>;
248		};
249
250		i2c_smb_3: i2c@40004c00 {
251			compatible = "microchip,xec-i2c";
252			reg = <0x40004C00 0x80>;
253			clock-frequency = <I2C_BITRATE_STANDARD>;
254			interrupts = <23 1>;
255			pcrs = <3 15>;
256			#address-cells = <1>;
257			#size-cells = <0>;
258			status = "disabled";
259			girq = <13>;
260			girq-bit = <3>;
261		};
262
263		i2c_smb_4: i2c@40005000 {
264			compatible = "microchip,xec-i2c";
265			reg = <0x40005000 0x80>;
266			clock-frequency = <I2C_BITRATE_STANDARD>;
267			interrupts = <158 1>;
268			pcrs = <3 20>;
269			#address-cells = <1>;
270			#size-cells = <0>;
271			status = "disabled";
272			girq = <13>;
273			girq-bit = <4>;
274		};
275
276		espi0: espi@400f3400 {
277			compatible = "microchip,xec-espi";
278			reg = <0x400f3400 0x400>;
279			interrupts = <11 3>, <15 3>, <7 3>, <16 3>;
280			#address-cells = <1>;
281			#size-cells = <0>;
282			status = "disabled";
283		};
284		espi_saf0: espi@40008000 {
285			compatible = "microchip,xec-espi-saf";
286			reg = < 0x40008000 0x400
287				0x40070000 0x400
288				0x40071000 0x400>;
289			#address-cells = <1>;
290			#size-cells = <0>;
291			status = "disabled";
292		};
293
294		timer0: timer@40000c00 {
295			compatible = "microchip,xec-timer";
296			clock-frequency = <48000000>;
297			reg = <0x40000c00 0x20>;
298			interrupts = <136 0>;
299			max-value = <0xFFFF>;
300			prescaler = <0>;
301			status = "disabled";
302			girqs = <23 0>;
303			pcrs = <1 30>;
304		};
305		timer1: timer@40000c20 {
306			compatible = "microchip,xec-timer";
307			clock-frequency = <48000000>;
308			reg = <0x40000c20 0x20>;
309			interrupts = <137 0>;
310			max-value = <0xFFFF>;
311			prescaler = <0>;
312			status = "disabled";
313			girqs = <23 1>;
314			pcrs = <1 31>;
315		};
316		/*
317		 * NOTE 1: timers 2 and 3 not implemented in MEC152x.
318		 * NOTE 2: When RTOS timer used as kernel timer, timer4 used
319		 * to provide high speed busy wait counter. Keep disabled to
320		 * prevent counter driver from claiming it.
321		 */
322		timer4: timer@40000c80 {
323			compatible = "microchip,xec-timer";
324			clock-frequency = <48000000>;
325			reg = <0x40000c80 0x20>;
326			interrupts = <140 0>;
327			max-value = <0xFFFFFFFF>;
328			prescaler = <0>;
329			girqs = <23 4>;
330			pcrs = <3 23>;
331			status = "disabled";
332		};
333		timer5: timer@40000ca0 {
334			compatible = "microchip,xec-timer";
335			clock-frequency = <48000000>;
336			reg = <0x40000ca0 0x20>;
337			interrupts = <141 0>;
338			max-value = <0xFFFFFFFF>;
339			prescaler = <0>;
340			girqs = <23 5>;
341			pcrs = <3 24>;
342		};
343		hibtimer0: timer@40009800 {
344			reg = <0x40009800 0x20>;
345			interrupts = <112 0>;
346			girqs = <23 16>;
347		};
348		hibtimer1: timer@40009820 {
349			reg = <0x40009820 0x20>;
350			interrupts = <113 0>;
351			girqs = <23 17>;
352		};
353		ps2_0: ps2@40009000 {
354			compatible = "microchip,xec-ps2";
355			reg = <0x40009000 0x40>;
356			interrupts = <100 1>;
357			girqs = <18 10>, <21 18>;
358			pcrs = <3 5>;
359			#address-cells = <1>;
360			#size-cells = <0>;
361			status = "disabled";
362		};
363		ps2_1: ps2@40009040 {
364			compatible = "microchip,xec-ps2";
365			reg = <0x40009040 0x40>;
366			interrupts = <101 1>;
367			girqs = <18 11>, <21 21>;
368			pcrs = <3 6>;
369			#address-cells = <1>;
370			#size-cells = <0>;
371			status = "disabled";
372		};
373		pwm0: pwm@40005800 {
374			compatible = "microchip,xec-pwm";
375			reg = <0x40005800 0x20>;
376			pcrs = <1 4>;
377			status = "disabled";
378			#pwm-cells = <3>;
379		};
380		pwm1: pwm@40005810 {
381			compatible = "microchip,xec-pwm";
382			reg = <0x40005810 0x20>;
383			pcrs = <1 20>;
384			status = "disabled";
385			#pwm-cells = <3>;
386		};
387		pwm2: pwm@40005820 {
388			compatible = "microchip,xec-pwm";
389			reg = <0x40005820 0x20>;
390			pcrs = <1 21>;
391			status = "disabled";
392			#pwm-cells = <3>;
393		};
394		pwm3: pwm@40005830 {
395			compatible = "microchip,xec-pwm";
396			reg = <0x40005830 0x20>;
397			pcrs = <1 22>;
398			status = "disabled";
399			#pwm-cells = <3>;
400		};
401		pwm4: pwm@40005840 {
402			compatible = "microchip,xec-pwm";
403			reg = <0x40005840 0x20>;
404			pcrs = <1 23>;
405			status = "disabled";
406			#pwm-cells = <3>;
407		};
408		pwm5: pwm@40005850 {
409			compatible = "microchip,xec-pwm";
410			reg = <0x40005850 0x20>;
411			pcrs = <1 24>;
412			status = "disabled";
413			#pwm-cells = <3>;
414		};
415		pwm6: pwm@40005860 {
416			compatible = "microchip,xec-pwm";
417			reg = <0x40005860 0x20>;
418			pcrs = <1 25>;
419			status = "disabled";
420			#pwm-cells = <3>;
421		};
422		pwm7: pwm@40005870 {
423			compatible = "microchip,xec-pwm";
424			reg = <0x40005870 0x20>;
425			pcrs = <1 26>;
426			status = "disabled";
427			#pwm-cells = <3>;
428		};
429		pwm8: pwm@40005880 {
430			compatible = "microchip,xec-pwm";
431			reg = <0x40005880 0x20>;
432			pcrs = <1 27>;
433			status = "disabled";
434			#pwm-cells = <3>;
435		};
436		adc0: adc@40007c00 {
437			compatible = "microchip,xec-adc";
438			reg = <0x40007c00 0x90>;
439			interrupts = <78 0>, <79 0>;
440			girqs = <17 8>, <17 9>;
441			pcrs = <3 3>;
442			status = "disabled";
443			#io-channel-cells = <1>;
444			clktime = <32>;
445			channels = <8>;
446		};
447		kbd0: kbd@40009c00 {
448			compatible = "microchip,xec-kbd";
449			reg = <0x40009c00 0x18>;
450			interrupts = <135 0>;
451			girqs = <21 25>;
452			pcrs = <3 11>;
453			status = "disabled";
454			#address-cells = <1>;
455			#size-cells = <0>;
456		};
457		peci0: peci@40006400 {
458			compatible = "microchip,xec-peci";
459			reg = <0x40006400 0x80>;
460			interrupts = <70 4>;
461			girqs = <17 0>;
462			pcrs = <1 1>;
463			#address-cells = <1>;
464			#size-cells = <0>;
465		};
466		spi0: spi@40070000 {
467			compatible = "microchip,xec-qmspi";
468			reg = <0x40070000 0x400>;
469			interrupts = <91 2>;
470			clock-frequency = <12000000>;
471			rxdma = <11>;
472			txdma = <10>;
473			lines = <1>;
474			chip_select = <0>;
475			dcsckon = <6>;
476			dckcsoff = <4>;
477			dldh = <6>;
478			dcsda = <6>;
479			#address-cells = <1>;
480			#size-cells = <0>;
481			status = "disabled";
482		};
483		tach0: tach@40006000 {
484			compatible = "microchip,xec-tach";
485			reg = <0x40006000 0x10>;
486			interrupts = <71 4>;
487			girqs = <17 1>;
488			pcrs = <1 2>;
489			status = "disabled";
490			#address-cells = <1>;
491			#size-cells = <0>;
492		};
493		tach1: tach@40006010 {
494			compatible = "microchip,xec-tach";
495			reg = <0x40006010 0x10>;
496			interrupts = <72 4>;
497			girqs = <17 2>;
498			pcrs = <1 11>;
499			status = "disabled";
500			#address-cells = <1>;
501			#size-cells = <0>;
502		};
503		tach2: tach@40006020 {
504			compatible = "microchip,xec-tach";
505			reg = <0x40006020 0x10>;
506			interrupts = <73 4>;
507			girqs = <17 3>;
508			pcrs = <1 12>;
509			status = "disabled";
510			#address-cells = <1>;
511			#size-cells = <0>;
512		};
513		tach3: tach@40006030 {
514			compatible = "microchip,xec-tach";
515			reg = <0x40006030 0x10>;
516			interrupts = <159 4>;
517			girqs = <17 4>;
518			pcrs = <1 13>;
519			status = "disabled";
520			#address-cells = <1>;
521			#size-cells = <0>;
522		};
523		bbled0: bbled@4000b800 {
524			reg = <0x4000b800 0x100>;
525			interrupts = <83 0>;
526			girqs = <17 13>;
527			pcrs = <3 16>;
528			status = "disabled";
529		};
530		bbled1: bbled@4000b900 {
531			reg = <0x4000b900 0x100>;
532			interrupts = <84 0>;
533			girqs = <17 14>;
534			pcrs = <3 17>;
535			status = "disabled";
536		};
537		bbled2: bbled@4000ba00 {
538			reg = <0x4000ba00 0x100>;
539			interrupts = <85 0>;
540			girqs = <17 15>;
541			pcrs = <3 18>;
542			status = "disabled";
543		};
544	};
545};
546
547&nvic {
548	arm,num-irq-priority-bits = <3>;
549};
550
551&systick {
552	status = "disabled";
553};
554