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Searched +full:pll +full:- +full:enable (Results 1 – 25 of 149) sorted by relevance

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/Zephyr-latest/drivers/clock_control/
DKconfig.lpc11u6x4 # SPDX-License-Identifier: Apache-2.0
12 Enable driver for reset and clock control used in
20 Enable SRAM1
25 Enable USB RAM
28 prompt "LPC11U6X PLL Clock source"
33 Use the internal oscillator as the clock source for the PLL
38 Use the system oscillator as the clock source for the PLL
DKconfig.beetle4 # SPDX-License-Identifier: Apache-2.0
13 Enable driver for Reset & Clock Control subsystem found
19 bool "PLL on Beetle"
22 Enable PLL on Beetle.
Dclock_stm32f0_f3.c5 * SPDX-License-Identifier: Apache-2.0
21 * @brief Set up pll configuration
29 * PLL MUL in config_pll_sysclock()
30 * 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000 in config_pll_sysclock()
31 * 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000 in config_pll_sysclock()
32 * 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000 in config_pll_sysclock()
34 * 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000 in config_pll_sysclock()
36 pll_mul = ((STM32_PLL_MULTIPLIER - 2) << RCC_CFGR_PLLMUL_Pos); in config_pll_sysclock()
39 * PLL PREDIV in config_pll_sysclock()
40 * 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000 in config_pll_sysclock()
[all …]
Dclock_stm32_ll_wba.c4 * SPDX-License-Identifier: Apache-2.0
62 return -ENOTSUP; in enabled_clock()
73 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
75 return -ENOTSUP; in stm32_clock_control_on()
78 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
79 pclken->enr); in stm32_clock_control_on()
81 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
94 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
96 return -ENOTSUP; in stm32_clock_control_off()
99 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
[all …]
Dclock_stm32l4_l5_wb_wl.c5 * SPDX-License-Identifier: Apache-2.0
30 * @brief Return PLL source
35 /* Configure PLL source */ in get_pll_source()
49 * @brief get the pll source frequency
69 * @brief Set up pll configuration
96 /* Enable the power interface clock */ in config_enable_default_clocks()
100 /* HW semaphore Clock enable */ in config_enable_default_clocks()
Dclock_stm32g4.c4 * SPDX-License-Identifier: Apache-2.0
22 * @brief Return PLL source
27 /* Configure PLL source */ in get_pll_source()
39 * @brief get the pll source frequency
55 * @brief Set up pll configuration
80 /* Enable the power interface clock */ in config_enable_default_clocks()
Dclock_stm32f2_f4_f7.c5 * SPDX-License-Identifier: Apache-2.0
22 * @brief Return PLL source
38 * @brief get the pll source frequency
76 /* Get the PLL I2S source : HSE or HSI */ in get_ck48_frequency()
80 /* Get the PLL I2S Q freq. No HAL macro for that */ in get_ck48_frequency()
94 * @brief Set up pll configuration
100 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
108 /* There is a Q divider on the PLL to configure the PLL48CK */ in config_pll_sysclock()
118 /* Enable the PLL (PLLON) before setting overdrive. Skipping the PLL in config_pll_sysclock()
120 * (ODSW) but the PLL clock system will be running during the locking in config_pll_sysclock()
[all …]
Dclock_stm32g0_u0.c6 * SPDX-License-Identifier: Apache-2.0
23 * @brief Return PLL source
28 /* Configure PLL source */ in get_pll_source()
40 * @brief get the pll source frequency
56 * @brief Set up pll configuration
76 /* Enable the power interface clock */ in config_enable_default_clocks()
Dclock_stm32_ll_h5.c7 * SPDX-License-Identifier: Apache-2.0
48 /** @brief returns the pll source frequency of given pll_id */
66 __ASSERT(0, "No PLL Source configured"); in get_pllsrc_frequency()
144 return -ENOTSUP; in enabled_clock()
155 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
157 return -ENOTSUP; in stm32_clock_control_on()
160 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
161 pclken->enr); in stm32_clock_control_on()
163 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
176 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
[all …]
Dclock_stm32l0_l1.c5 * SPDX-License-Identifier: Apache-2.0
29 * @brief Return PLL source
34 /* Configure PLL source */ in get_pll_source()
46 * @brief get the pll source frequency
62 * @brief Set up pll configuration
109 /* Enable System Configuration Controller clock. */ in config_enable_default_clocks()
Dclock_stm32_ll_common.c2 * Copyright (c) 2017-2022 Linaro Limited.
5 * SPDX-License-Identifier: Apache-2.0
76 #define RCC_PLLP_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)
81 #define RCC_PLLQ_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)
87 * @brief Return frequency for pll with 2 dividers and a multiplier
136 r = -ENOTSUP; in enabled_clock()
150 r = -ENOTSUP; in enabled_clock()
157 r = -ENOTSUP; in enabled_clock()
164 r = -ENOTSUP; in enabled_clock()
171 r = -ENOTSUP; in enabled_clock()
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/Zephyr-latest/dts/bindings/mipi-dsi/
Dst,stm32-mipi-dsi.yaml4 # SPDX-License-Identifier: Apache-2.0
9 compatible: "st,stm32-mipi-dsi"
11 include: [mipi-dsi-host.yaml, reset-device.yaml]
17 clock-names:
20 "dsiclk" DSI clock enable.
28 hs-active-high:
33 vs-active-high:
38 de-active-high:
41 DSI host data enable is active high.
43 loosely-packed:
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/Zephyr-latest/dts/bindings/clock/
Dsilabs,series2-hfrcodpll.yaml1 compatible: "silabs,series2-hfrcodpll"
4 Silicon Labs HFRCODPLL peripheral (high-frequency RC oscillator with digital phase-locked loop).
5 Can be used as a free-running RC oscillator or with PLL lock to the crystal oscillators HFXO
6 or LFXO. To enable PLL, set the `clocks` property to the source crystal oscillator, and set
7 the `dpll-*` options to desired values.
9 In PLL mode, `clock-frequency` represents the target PLL frequency.
10 In free-running mode, `clock-frequency` represents the HFRCO band to use.
12 include: fixed-clock.yaml
15 dpll-n:
18 dpll-m:
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Dst,stm32-msi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32-msi-clock"
8 include: [clock-controller.yaml, base.yaml]
11 msi-range:
18 - 0 # range 0 around 100 kHz
19 - 1 # range 1 around 200 kHz
20 - 2 # range 2 around 400 kHz
21 - 3 # range 3 around 800 kHz
22 - 4 # range 4 around 1M Hz
23 - 5 # range 5 around 2 MHz
[all …]
Dmicrochip,xec-pcr.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
25 pll-32k-src:
28 description: 32 KHz clock source for PLL
30 periph-32k-src:
35 xtal-single-ended:
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/Zephyr-latest/soc/ite/ec/it8xxx2/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
34 /* PLL Frequency Auto-Calibration Control 0 Register */
44 /* PLL Frequency Auto-Calibration Control 2 Register */
79 return -ERANGE; in chip_get_pll_freq()
92 * This load operation will ensure PLL setting is taken into in chip_pll_ctrl()
121 * PLL frequency setting = 4 (48MHz)
122 * MCU div = 0 (PLL / 1 = 48 mhz)
123 * FND div = 0 (PLL / 1 = 48 mhz)
124 * USB div = 0 (PLL / 1 = 48 mhz)
[all …]
/Zephyr-latest/soc/nxp/imx/imx8m/m7/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
17 /* OSC/PLL is already initialized by ROM and Cortex-A53 (u-boot) */
32 * The M7 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in SOC_RdcInit()
46 /* Enable the CCGR gate for SysPLL1 in Domain 1 */ in SOC_RdcInit()
48 /* Enable the CCGR gate for SysPLL2 in Domain 1 */ in SOC_RdcInit()
50 /* Enable the CCGR gate for SysPLL3 in Domain 1 */ in SOC_RdcInit()
53 /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ in SOC_RdcInit()
61 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
69 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
[all …]
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dsoc.c2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
61 /* Numerator of the Audio PLL fractional loop divider is 0 */
63 /* Denominator of the Audio PLL fractional loop divider is 1 */
152 /* enable usb ip clock */ in usb_device_clock_init()
157 /* enable usb ram clock */ in usb_device_clock_init()
159 /* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */ in usb_device_clock_init()
174 /* enable usb1 host clock */ in usb_device_clock_init()
176 /* Wait until host_needclk de-asserts */ in usb_device_clock_init()
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/
Dpower.c5 * SPDX-License-Identifier: Apache-2.0
27 * Lower power dissipation, 48MHz PLL is off
30 * between 16 to 25 MHz. Minimum 3ms until PLL reaches lock
34 * We touch the Cortex-M's primary mask and base priority registers
43 * PLL. Firmware should not disable JTAG/SWD in the EC subsystem
45 * TAP controller in a state of requesting clocks preventing the PLL
65 * Enable deep sleep mode in CM4 and MEC172x. in z_power_soc_deep_sleep()
66 * Enable CM4 deep sleep and sleep signals assertion on WFI. in z_power_soc_deep_sleep()
67 * Set MCHP Heavy sleep (PLL OFF when all CLK_REQ clear) and SLEEP_ALL in z_power_soc_deep_sleep()
72 SCB->SCR |= BIT(2); in z_power_soc_deep_sleep()
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/
Dtest_stm32_clock_configuration.c4 * SPDX-License-Identifier: Apache-2.0
40 "Expected sysclk src: PLL (0x%x). Actual: 0x%x", in ZTEST()
71 "Expected PLL src: HSE (%d). Actual PLL src: %d", in ZTEST()
76 "Expected PLL src: HSI (%d). Actual PLL src: %d", in ZTEST()
80 "Expected PLL src: HSI (%d). Actual PLL src: %d", in ZTEST()
85 "Expected PLL src: MSI (%d). Actual PLL src: %d", in ZTEST()
87 #else /* --> RCC_PLLSOURCE_NONE */ in ZTEST()
93 /* check RCC_CR_PLLON bit to enable/disable the PLL, but no status function exist */ in ZTEST()
94 if (READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) { in ZTEST()
95 /* should not happen : PLL must be disabled when not used */ in ZTEST()
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/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dlpm_rt1064.c4 * SPDX-License-Identifier: Apache-2.0
66 while ((CCM->CDHIPR & ((1UL << busy_shift))) != 0UL) { in clock_set_mux()
88 while ((CCM->CDHIPR & ((uint32_t)(1UL << busy_shift))) != 0UL) { in clock_set_div()
101 /* Bypass PLL first */ in clock_init_usb1_pll()
102 CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) | in clock_init_usb1_pll()
103 CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src); in clock_init_usb1_pll()
105 CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) | in clock_init_usb1_pll()
108 CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); in clock_init_usb1_pll()
110 while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0UL) { in clock_init_usb1_pll()
115 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; in clock_init_usb1_pll()
[all …]
/Zephyr-latest/soc/nxp/imxrt/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
15 # Note- When SECOND_CORE_MCUX is set, the dependencies for this Kconfig
23 Enable data structures required by the boot ROM to boot the
104 Enable access to external SDRAM region managed by the SEMC. This
112 Enable access to external HYPERRAM region managed by the FLEXSPI.
122 by booting an image targeting the Cortex-M4 from the Cortex-M7 CPU.
142 bool "Initialize ARM PLL"
145 bool "Initialize Video PLL"
150 If y, the Ethernet PLL is initialized. Always enabled on e.g.
151 MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection
[all …]
/Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
17 /* OSC/PLL is already initialized by ROM and Cortex-A53 (u-boot) */
27 * The M4 core is running at domain 1, enable clock gate for in SOC_RdcInit()
39 * The M4 core is running at domain 1, enable the PLL clock sources in SOC_RdcInit()
42 /* Enable SysPLL1 to Domain 1 */ in SOC_RdcInit()
44 /* Enable SysPLL2 to Domain 1 */ in SOC_RdcInit()
46 /* Enable SysPLL3 to Domain 1 */ in SOC_RdcInit()
48 /* Enable AudioPLL1 to Domain 1 */ in SOC_RdcInit()
50 /* Enable AudioPLL2 to Domain 1 */ in SOC_RdcInit()
[all …]
/Zephyr-latest/soc/nxp/imxrt/imxrt6xx/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
41 bool "Initialize SYS PLL"
44 bool "Initialize Audio PLL"
62 Enable code cache for FlexSPI region at boot. If this Kconfig is
/Zephyr-latest/dts/bindings/can/
Dmicrochip,mcp251xfd.yaml2 # SPDX-License-Identifier: Apache-2.0
11 cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>;
17 spi-max-frequency = <18000000>;
18 int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>;
20 osc-freq = <40000000>;
27 include: [spi-device.yaml, can-fd-controller.yaml]
30 osc-freq:
35 int-gpios:
36 type: phandle-array
39 The interrupt signal from the controller is active low in push-pull mode.
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