Lines Matching +full:pll +full:- +full:enable
4 * SPDX-License-Identifier: Apache-2.0
62 return -ENOTSUP; in enabled_clock()
73 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
75 return -ENOTSUP; in stm32_clock_control_on()
78 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
79 pclken->enr); in stm32_clock_control_on()
81 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
94 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
96 return -ENOTSUP; in stm32_clock_control_off()
99 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
100 pclken->enr); in stm32_clock_control_off()
117 err = enabled_clock(pclken->bus); in stm32_clock_control_configure()
123 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr), in stm32_clock_control_configure()
124 STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr)); in stm32_clock_control_configure()
125 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr), in stm32_clock_control_configure()
126 STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr)); in stm32_clock_control_configure()
131 return -ENOTSUP; in stm32_clock_control_configure()
145 __ASSERT(0, "No PLL Source configured"); in get_pllsrc_frequency()
159 __ASSERT(0, "No PLL Source configured"); in get_pllsrc()
183 /* PLL is the SYSCLK source, use 'ahb5-prescaler' */ in stm32_clock_control_get_subsys_rate()
187 /* PLL is not the SYSCLK source, use 'ahb5-div'(if set) */ in stm32_clock_control_get_subsys_rate()
198 switch (pclken->bus) { in stm32_clock_control_get_subsys_rate()
271 return -ENOTSUP; in stm32_clock_control_get_subsys_rate()
274 if (pclken->div) { in stm32_clock_control_get_subsys_rate()
275 *rate /= (pclken->div + 1); in stm32_clock_control_get_subsys_rate()
288 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == true) { in stm32_clock_control_get_status()
290 if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr) in stm32_clock_control_get_status()
291 == pclken->enr) { in stm32_clock_control_get_status()
298 if (enabled_clock(pclken->bus) == 0) { in stm32_clock_control_get_status()
326 return -ERANGE; in get_vco_input_range()
349 /* Enable HSI if not enabled */ in stm32_clock_switch_to_hsi()
351 /* Enable HSI */ in stm32_clock_switch_to_hsi()
365 * Re-enable HSE clock if required after switch source to HSI in stm32_clock_switch_to_hsi()
372 /* Enable HSE */ in stm32_clock_switch_to_hsi()
389 /* Configure PLL source */ in set_up_plls()
392 /* Main PLL configuration and activation */ in set_up_plls()
395 /* Main PLL configuration and activation */ in set_up_plls()
398 return -ENOTSUP; in set_up_plls()
430 /* Enable PLL */ in set_up_plls()
433 /* Wait for PLL ready */ in set_up_plls()
436 /* Init PLL source to None */ in set_up_plls()
451 /* Enable HSE */ in set_up_fixed_clock_sources()
459 /* Enable HSI if not enabled */ in set_up_fixed_clock_sources()
461 /* Enable HSI */ in set_up_fixed_clock_sources()
470 /* LSI belongs to the back-up domain, enable access.*/ in set_up_fixed_clock_sources()
486 /* LSE belongs to the back-up domain, enable access.*/ in set_up_fixed_clock_sources()
497 /* Enable LSE Oscillator (32.768 kHz) */ in set_up_fixed_clock_sources()
503 /* Enable LSESYS additionally */ in set_up_fixed_clock_sources()
514 * This routine is called to enable and configure the clocks and PLL
532 /* In case of chainloaded application, it may happen that PLL in stm32_clock_control_init()
550 /* If required, apply max step freq for Sysclock w/ PLL input */ in stm32_clock_control_init()
575 /* PLL is the SYSCLK source, use 'ahb5-prescaler' */ in stm32_clock_control_init()
578 /* PLL is not the SYSCLK source, use 'ahb5-div'(if set) */ in stm32_clock_control_init()
587 /* Set PLL as System Clock Source */ in stm32_clock_control_init()