1# Copyright (c) 2020 Abram Early
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  Microchip MCP251XFD SPI CAN FD controller
6
7  The MCP251XFD node is defined on an SPI bus. An example
8  configuration is:
9
10  &mikrobus_spi {
11      cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>;
12
13      mcp2518fd_mikroe_mcp2518fd_click: mcp2518fd@0 {
14          compatible = "microchip,mcp251xfd";
15          status = "okay";
16
17          spi-max-frequency = <18000000>;
18          int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>;
19          reg = <0x0>;
20          osc-freq = <40000000>;
21
22      };
23  };
24
25compatible: "microchip,mcp251xfd"
26
27include: [spi-device.yaml, can-fd-controller.yaml]
28
29properties:
30  osc-freq:
31    type: int
32    required: true
33    description: Frequency of the external oscillator in Hz.
34
35  int-gpios:
36    type: phandle-array
37    required: true
38    description: |
39      The interrupt signal from the controller is active low in push-pull mode.
40      The property value should ensure the flags properly describe the signal
41      that is presented to the driver.
42
43  pll-enable:
44    type: boolean
45    description: |
46      Enables controller PLL, which multiplies input clock frequency by 10.
47      This parameter also implicitly sets whether the clock is from the PLL
48      output or directly from the oscillator.
49      If this option is enabled the clock source is the PLL, otherwise its
50      the oscillator.
51
52  timestamp-prescaler:
53    type: int
54    default: 1
55    description: |
56      Prescaler value for computing the timestamps of received messages.
57      The timestamp counter is derived from the internal clock divided by this value.
58      Valid range is [1, 1024].
59
60  sof-on-clko:
61    type: boolean
62    description: |
63      Output start-of-frame (SOF) signal on the CLKO pin every time
64      a Start bit of a CAN message is transmitted or received. If this option
65      is not set, then an internal clock (typically 40MHz or 20MHz) will be
66      output on CLKO pin instead.
67
68  clko-div:
69    type: int
70    description: The factor to divide the system clock for CLKO pin.
71    default: 10
72    enum:
73      - 1
74      - 2
75      - 4
76      - 10
77