2  * Copyright (c) 2017-2022 Linaro Limited.
5  * SPDX-License-Identifier: Apache-2.0
76 #define RCC_PLLP_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)
81 #define RCC_PLLQ_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)
87  * @brief Return frequency for pll with 2 dividers and a multiplier
136 			r = -ENOTSUP;  in enabled_clock()
150 			r = -ENOTSUP;  in enabled_clock()
157 			r = -ENOTSUP;  in enabled_clock()
164 			r = -ENOTSUP;  in enabled_clock()
171 			r = -ENOTSUP;  in enabled_clock()
178 			r = -ENOTSUP;  in enabled_clock()
185 			r = -ENOTSUP;  in enabled_clock()
192 			r = -ENOTSUP;  in enabled_clock()
199 			r = -ENOTSUP;  in enabled_clock()
206 			r = -ENOTSUP;  in enabled_clock()
213 			r = -ENOTSUP;  in enabled_clock()
220 			r = -ENOTSUP;  in enabled_clock()
227 			r = -ENOTSUP;  in enabled_clock()
234 			r = -ENOTSUP;  in enabled_clock()
241 			r = -ENOTSUP;  in enabled_clock()
246 		return -ENOTSUP;  in enabled_clock()
260 	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {  in stm32_clock_control_on()
262 		return -ENOTSUP;  in stm32_clock_control_on()
265 	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,  in stm32_clock_control_on()
266 		     pclken->enr);  in stm32_clock_control_on()
270 	temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);  in stm32_clock_control_on()
283 	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {  in stm32_clock_control_off()
285 		return -ENOTSUP;  in stm32_clock_control_off()
288 	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,  in stm32_clock_control_off()
289 		       pclken->enr);  in stm32_clock_control_off()
306 	err = enabled_clock(pclken->bus);  in stm32_clock_control_configure()
312 	if (pclken->enr == NO_SEL) {  in stm32_clock_control_configure()
317 	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),  in stm32_clock_control_configure()
318 		       STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));  in stm32_clock_control_configure()
319 	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),  in stm32_clock_control_configure()
320 		     STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));  in stm32_clock_control_configure()
325 	return -ENOTSUP;  in stm32_clock_control_configure()
357 	if (pclken->bus == STM32_SRC_PCLK) {  in stm32_clock_control_get_subsys_rate()
360 		return -ENOTSUP;  in stm32_clock_control_get_subsys_rate()
366 	switch (pclken->bus) {  in stm32_clock_control_get_subsys_rate()
406 			return -EIO;  in stm32_clock_control_get_subsys_rate()
491 		return -ENOTSUP;  in stm32_clock_control_get_subsys_rate()
494 	if (pclken->div) {  in stm32_clock_control_get_subsys_rate()
495 		*rate /= (pclken->div + 1);  in stm32_clock_control_get_subsys_rate()
508 	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == true) {  in stm32_clock_control_get_status()
510 		if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)  in stm32_clock_control_get_status()
511 		    == pclken->enr) {  in stm32_clock_control_get_status()
518 		if (enabled_clock(pclken->bus) == 0) {  in stm32_clock_control_get_status()
540 	/* Enable HSI if not enabled */  in stm32_clock_switch_to_hsi()
542 		/* Enable HSI */  in stm32_clock_switch_to_hsi()
561 	 * Case of chain-loaded applications:  in set_up_plls()
562 	 * Switch to HSI and disable the PLL before configuration.  in set_up_plls()
564 	 * case we're currently running from the PLL we're about to  in set_up_plls()
572 	/* Disable PLL */  in set_up_plls()
575 		/* Wait for PLL to be disabled */  in set_up_plls()
583 	 * and disabling PLL, but before enabling PLL again,  in set_up_plls()
584 	 * since PLL source can be PLL2.  in set_up_plls()
593 	/* Enable PLL2 */  in set_up_plls()
603 	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, pllp(STM32_PLL_P_DIVISOR));  in set_up_plls()
607 	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, pllq(STM32_PLL_Q_DIVISOR));  in set_up_plls()
613 	/* Enable PLL */  in set_up_plls()
616 	/* Wait for PLL ready */  in set_up_plls()
624 	/* Enable PLL */  in set_up_plls()
627 		/* Wait for PLL ready */  in set_up_plls()
637 		/* Check if need to enable HSE bypass feature or not */  in set_up_fixed_clock_sources()
650 		/* Enable HSE */  in set_up_fixed_clock_sources()
655 		/* Check if we need to enable HSE clock security system or not */  in set_up_fixed_clock_sources()
663 		/* Enable HSI if not enabled */  in set_up_fixed_clock_sources()
665 			/* Enable HSI */  in set_up_fixed_clock_sources()
690 		/* Enable MSI hardware auto calibration */  in set_up_fixed_clock_sources()
696 		/* Enable MSI if not enabled */  in set_up_fixed_clock_sources()
698 			/* Enable MSI */  in set_up_fixed_clock_sources()
720 		/* LSE belongs to the back-up domain, enable access.*/  in set_up_fixed_clock_sources()
742 		/* Enable LSE Oscillator (32.768 kHz) */  in set_up_fixed_clock_sources()
786 		 * No-op on other series.  in set_up_fixed_clock_sources()
800  * This routine is called to enable and configure the clocks and PLL
848 	/* Set PLL as System Clock Source */  in stm32_clock_control_init()