Lines Matching +full:pll +full:- +full:enable

5  * SPDX-License-Identifier: Apache-2.0
22  * @brief Return PLL source
38  * @brief get the pll source frequency
76 		/* Get the PLL I2S source : HSE or HSI */  in get_ck48_frequency()
80 		/* Get the PLL I2S Q freq. No HAL macro for that */  in get_ck48_frequency()
94  * @brief Set up pll configuration
100 	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, pllr(STM32_PLL_R_DIVISOR));  in config_pll_sysclock()
108 	/* There is a Q divider on the PLL to configure the PLL48CK */  in config_pll_sysclock()
118 		/* Enable the PLL (PLLON) before setting overdrive. Skipping the PLL  in config_pll_sysclock()
120 		 * (ODSW) but the PLL clock system will be running during the locking  in config_pll_sysclock()
122 		 * Sub section: Entering Over-drive mode.  in config_pll_sysclock()
136 		/* The PLL could still not be locked when returning to the caller  in config_pll_sysclock()
137 		 * function. But the caller doesn't know we've turned on the PLL  in config_pll_sysclock()
138 		 * for the overdrive function. The caller will try to turn on the PLL  in config_pll_sysclock()
139 		 * And start waiting for the PLL locking phase to complete.  in config_pll_sysclock()
150  * @brief Set up PLL I2S configuration