1 /*
2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 */
7
8 #include <zephyr/arch/riscv/csr.h>
9 #include <zephyr/kernel.h>
10 #include <zephyr/device.h>
11 #include <zephyr/init.h>
12 #include "ilm.h"
13 #include <soc_common.h>
14 #include "soc_espi.h"
15 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
16
17 /*
18 * This define gets the total number of USBPD ports available on the
19 * ITE EC chip from dtsi (include status disable). Both it81202 and
20 * it81302 support two USBPD ports.
21 */
22 #define SOC_USBPD_ITE_PHY_PORT_COUNT \
23 COND_CODE_1(DT_NODE_EXISTS(DT_INST(1, ite_it8xxx2_usbpd)), (2), (1))
24
25 /*
26 * This define gets the number of active USB Power Delivery (USB PD)
27 * ports in use on the ITE microcontroller from dts (only status okay).
28 * The active port usage should follow the order of ITE TCPC port index,
29 * ex. if we're active only one ITE USB PD port, then the port should be
30 * 0x3700 (port0 register base), instead of 0x3800 (port1 register base).
31 */
32 #define SOC_USBPD_ITE_ACTIVE_PORT_COUNT DT_NUM_INST_STATUS_OKAY(ite_it8xxx2_usbpd)
33
34 /* PLL Frequency Auto-Calibration Control 0 Register */
35 #define PLL_FREQ_AUTO_CAL_EN BIT(7)
36 #define LOCK_TUNING_FACTORS_OF_LCO BIT(3)
37 /* LC Oscillator Control Register */
38 #define LCO_Power_CTRL BIT(1)
39 /* LC Oscillator Control Register 1 */
40 #define LDO_Power_CTRL BIT(1)
41 /* LC Oscillator Tuning Factor 2 */
42 #define LCO_SC_FACTOR_MASK GENMASK(6, 4)
43 #define LCO_SC_FACTOR(n) FIELD_PREP(LCO_SC_FACTOR_MASK, n)
44 /* PLL Frequency Auto-Calibration Control 2 Register */
45 #define AUTO_CAL_ENABLE BIT(1)
46 #define PLL_FREQ_AUTO_CAL_START BIT(0)
47 #define AUTO_CAL_ENABLE_AND_START (AUTO_CAL_ENABLE | PLL_FREQ_AUTO_CAL_START)
48
chip_get_pll_freq(void)49 uint32_t chip_get_pll_freq(void)
50 {
51 uint32_t pllfreq;
52
53 switch (IT8XXX2_ECPM_PLLFREQR & 0x0F) {
54 case 0:
55 pllfreq = MHZ(8);
56 break;
57 case 1:
58 pllfreq = MHZ(16);
59 break;
60 case 2:
61 pllfreq = MHZ(24);
62 break;
63 case 3:
64 pllfreq = MHZ(32);
65 break;
66 case 4:
67 pllfreq = MHZ(48);
68 break;
69 case 5:
70 pllfreq = MHZ(64);
71 break;
72 case 6:
73 pllfreq = MHZ(72);
74 break;
75 case 7:
76 pllfreq = MHZ(96);
77 break;
78 default:
79 return -ERANGE;
80 }
81
82 return pllfreq;
83 }
84
chip_pll_ctrl(enum chip_pll_mode mode)85 void __soc_ram_code chip_pll_ctrl(enum chip_pll_mode mode)
86 {
87 volatile uint8_t _pll_ctrl __unused;
88
89 IT8XXX2_ECPM_PLLCTRL = mode;
90 /*
91 * for deep doze / sleep mode
92 * This load operation will ensure PLL setting is taken into
93 * control register before wait for interrupt instruction.
94 */
95 _pll_ctrl = IT8XXX2_ECPM_PLLCTRL;
96 }
97
98 #ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
99 struct pll_config_t {
100 uint8_t pll_freq;
101 uint8_t div_mcu;
102 uint8_t div_fnd;
103 uint8_t div_usb;
104 uint8_t div_uart;
105 uint8_t div_smb;
106 uint8_t div_sspi;
107 uint8_t div_ec;
108 uint8_t div_jtag;
109 uint8_t div_pwm;
110 uint8_t div_usbpd;
111 };
112
113 enum pll_frequency {
114 PLL_FREQ_48M = 0,
115 PLL_FREQ_96M,
116 PLL_FREQ_CNT
117 };
118
119 static const struct pll_config_t pll_configuration[PLL_FREQ_CNT] = {
120 /*
121 * PLL frequency setting = 4 (48MHz)
122 * MCU div = 0 (PLL / 1 = 48 mhz)
123 * FND div = 0 (PLL / 1 = 48 mhz)
124 * USB div = 0 (PLL / 1 = 48 mhz)
125 * UART div = 1 (PLL / 2 = 24 mhz)
126 * SMB div = 1 (PLL / 2 = 24 mhz)
127 * SSPI div = 1 (PLL / 2 = 24 mhz)
128 * EC div = 6 (FND / 6 = 8 mhz)
129 * JTAG div = 1 (PLL / 2 = 24 mhz)
130 * PWM div = 0 (PLL / 1 = 48 mhz)
131 * USBPD div = 5 (PLL / 6 = 8 mhz)
132 */
133 [PLL_FREQ_48M] = {.pll_freq = 4,
134 .div_mcu = 0,
135 .div_fnd = 0,
136 .div_usb = 0,
137 .div_uart = 1,
138 .div_smb = 1,
139 .div_sspi = 1,
140 #ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
141 .div_ec = 1,
142 #else
143 .div_ec = 6,
144 #endif
145 .div_jtag = 1,
146 .div_pwm = 0,
147 .div_usbpd = 5},
148 /*
149 * PLL frequency setting = 7 (96MHz)
150 * MCU div = 1 (PLL / 2 = 48 mhz)
151 * FND div = 1 (PLL / 2 = 48 mhz)
152 * USB div = 1 (PLL / 2 = 48 mhz)
153 * UART div = 3 (PLL / 4 = 24 mhz)
154 * SMB div = 3 (PLL / 4 = 24 mhz)
155 * SSPI div = 3 (PLL / 4 = 24 mhz)
156 * EC div = 6 (FND / 6 = 8 mhz)
157 * JTAG div = 3 (PLL / 4 = 24 mhz)
158 * PWM div = 1 (PLL / 2 = 48 mhz)
159 * USBPD div = 11 (PLL / 12 = 8 mhz)
160 */
161 [PLL_FREQ_96M] = {.pll_freq = 7,
162 .div_mcu = 1,
163 .div_fnd = 1,
164 .div_usb = 1,
165 .div_uart = 3,
166 .div_smb = 3,
167 .div_sspi = 3,
168 #ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
169 .div_ec = 1,
170 #else
171 .div_ec = 6,
172 #endif
173 .div_jtag = 3,
174 .div_pwm = 1,
175 .div_usbpd = 11},
176 };
177
chip_run_pll_sequence(const struct pll_config_t * pll)178 void __soc_ram_code chip_run_pll_sequence(const struct pll_config_t *pll)
179 {
180 /* Enable HW timer to wakeup chip from the sleep mode */
181 timer_5ms_one_shot();
182 /*
183 * Configure PLL clock dividers.
184 * Writing data to these registers doesn't change the
185 * PLL frequency immediately until the status is changed
186 * into wakeup from the sleep mode.
187 * The following code is intended to make the system
188 * enter sleep mode, and wait HW timer to wakeup chip to
189 * complete PLL update.
190 */
191 IT8XXX2_ECPM_PLLFREQR = pll->pll_freq;
192 /* Pre-set FND clock frequency = PLL / 3 */
193 IT8XXX2_ECPM_SCDCR0 = (2 << 4);
194 /* JTAG and EC */
195 IT8XXX2_ECPM_SCDCR3 = (pll->div_jtag << 4) | pll->div_ec;
196 /* Chip sleep after wait for interrupt (wfi) instruction */
197 chip_pll_ctrl(CHIP_PLL_SLEEP);
198 /* Chip sleep and wait timer wake it up */
199 __asm__ volatile ("wfi");
200 /* New FND and MCU clock frequency */
201 IT8XXX2_ECPM_SCDCR0 = (pll->div_fnd << 4) | pll->div_mcu;
202 /* Chip doze after wfi instruction */
203 chip_pll_ctrl(CHIP_PLL_DOZE);
204 /* USB and UART */
205 IT8XXX2_ECPM_SCDCR1 = (pll->div_usb << 4) | pll->div_uart;
206 /* SSPI and SMB */
207 IT8XXX2_ECPM_SCDCR2 = (pll->div_sspi << 4) | pll->div_smb;
208 /* USBPD and PWM */
209 IT8XXX2_ECPM_SCDCR4 = (pll->div_usbpd << 4) | pll->div_pwm;
210 }
211
chip_configure_pll(const struct pll_config_t * pll)212 static void chip_configure_pll(const struct pll_config_t *pll)
213 {
214 /* Re-configure PLL clock or not. */
215 if (((IT8XXX2_ECPM_PLLFREQR & 0xf) != pll->pll_freq) ||
216 ((IT8XXX2_ECPM_SCDCR0 & 0xf0) != (pll->div_fnd << 4)) ||
217 ((IT8XXX2_ECPM_SCDCR3 & 0xf) != pll->div_ec)) {
218 #ifdef CONFIG_ESPI
219 /*
220 * We have to disable eSPI pad before changing
221 * PLL sequence or sequence will fail if CS# pin is low.
222 */
223 espi_it8xxx2_enable_pad_ctrl(ESPI_IT8XXX2_SOC_DEV, false);
224 #endif
225 /* Run change PLL sequence */
226 chip_run_pll_sequence(pll);
227 #ifdef CONFIG_ESPI
228 /* Enable eSPI pad after changing PLL sequence */
229 espi_it8xxx2_enable_pad_ctrl(ESPI_IT8XXX2_SOC_DEV, true);
230 #endif
231 }
232 }
233
chip_change_pll(void)234 static int chip_change_pll(void)
235 {
236
237 if (IS_ENABLED(CONFIG_HAS_ITE_INTC)) {
238 ite_intc_save_and_disable_interrupts();
239 }
240
241 /* Disable auto calibration before setting PLL frequency */
242 if (IT8XXX2_ECPM_PFACC0R & PLL_FREQ_AUTO_CAL_EN) {
243 IT8XXX2_ECPM_PFACC0R &= ~PLL_FREQ_AUTO_CAL_EN;
244 }
245
246 /* configure PLL/CPU/flash clock */
247 if (IS_ENABLED(CONFIG_SOC_IT8XXX2_LCVCO)) {
248 chip_configure_pll(&pll_configuration[PLL_FREQ_96M]);
249
250 /* Enable LCVCO calibration */
251 IT8XXX2_ECPM_PFACC1R = 0x01;
252 IT8XXX2_ECPM_PFACC0R |= (PLL_FREQ_AUTO_CAL_EN | LOCK_TUNING_FACTORS_OF_LCO);
253 IT8XXX2_ECPM_LCOCR |= LCO_Power_CTRL;
254 IT8XXX2_ECPM_LCOCR1 |= LDO_Power_CTRL;
255 IT8XXX2_ECPM_LCOTF2 &= ~LCO_SC_FACTOR_MASK;
256 IT8XXX2_ECPM_LCOTF2 |= LCO_SC_FACTOR(2);
257 IT8XXX2_ECPM_PFACC2R = AUTO_CAL_ENABLE_AND_START;
258 } else {
259 chip_configure_pll(&pll_configuration[PLL_FREQ_48M]);
260 }
261 if (IS_ENABLED(CONFIG_HAS_ITE_INTC)) {
262 ite_intc_restore_interrupts();
263 }
264
265 return 0;
266 }
267 SYS_INIT(chip_change_pll, PRE_KERNEL_1, CONFIG_IT8XXX2_PLL_SEQUENCE_PRIORITY);
268 BUILD_ASSERT(CONFIG_FLASH_INIT_PRIORITY < CONFIG_IT8XXX2_PLL_SEQUENCE_PRIORITY,
269 "CONFIG_FLASH_INIT_PRIORITY must be less than CONFIG_IT8XXX2_PLL_SEQUENCE_PRIORITY");
270 #endif /* CONFIG_SOC_IT8XXX2_PLL_FLASH_48M */
271
272 #ifdef CONFIG_SOC_IT8XXX2_CPU_IDLE_GATING
273 /* Preventing CPU going into idle mode during command queue. */
274 static atomic_t cpu_idle_disabled;
275
chip_permit_idle(void)276 void chip_permit_idle(void)
277 {
278 atomic_dec(&cpu_idle_disabled);
279 }
280
chip_block_idle(void)281 void chip_block_idle(void)
282 {
283 atomic_inc(&cpu_idle_disabled);
284 }
285
cpu_idle_not_allowed(void)286 bool cpu_idle_not_allowed(void)
287 {
288 return !!(atomic_get(&cpu_idle_disabled));
289 }
290 #endif
291
292 /* The routine must be called with interrupts locked */
riscv_idle(enum chip_pll_mode mode,unsigned int key)293 void riscv_idle(enum chip_pll_mode mode, unsigned int key)
294 {
295 /*
296 * The routine is called with interrupts locked (in kernel/idle()).
297 * But on kernel/context test_kernel_cpu_idle test, the routine will be
298 * called without interrupts locked. Hence we disable M-mode external
299 * interrupt here to protect the below content.
300 */
301 csr_clear(mie, MIP_MEIP);
302 sys_trace_idle();
303 #ifdef CONFIG_ESPI
304 /*
305 * H2RAM feature requires RAM clock to be active. Since the below doze
306 * mode will disable CPU and RAM clocks, enable eSPI transaction
307 * interrupt to restore clocks. With this interrupt, EC will not defer
308 * eSPI bus while transaction is accepted.
309 */
310 espi_it8xxx2_enable_trans_irq(ESPI_IT8XXX2_SOC_DEV, true);
311 #endif
312 /* Chip doze after wfi instruction */
313 chip_pll_ctrl(mode);
314
315 do {
316 #ifndef CONFIG_SOC_IT8XXX2_JTAG_DEBUG_INTERFACE
317 /* Wait for interrupt */
318 __asm__ volatile ("wfi");
319 #endif
320 /*
321 * Sometimes wfi instruction may fail due to CPU's MTIP@mip
322 * register is non-zero.
323 * If the ite_intc_no_irq() is true at this point,
324 * it means that EC waked-up by the above issue not an
325 * interrupt. Hence we loop running wfi instruction here until
326 * wfi success.
327 */
328 } while (ite_intc_no_irq());
329
330 if (IS_ENABLED(CONFIG_SOC_IT8XXX2_LCVCO)) {
331 if (mode != CHIP_PLL_DOZE) {
332 IT8XXX2_ECPM_PFACC2R |= PLL_FREQ_AUTO_CAL_START;
333 }
334 }
335
336 #ifdef CONFIG_ESPI
337 /* CPU has been woken up, the interrupt is no longer needed */
338 espi_it8xxx2_enable_trans_irq(ESPI_IT8XXX2_SOC_DEV, false);
339 #endif
340 /*
341 * Enable M-mode external interrupt
342 * An interrupt can not be fired yet until we enable global interrupt
343 */
344 csr_set(mie, MIP_MEIP);
345 /* Restore global interrupt lockout state */
346 irq_unlock(key);
347 }
348
arch_cpu_idle(void)349 void arch_cpu_idle(void)
350 {
351 #ifdef CONFIG_SOC_IT8XXX2_CPU_IDLE_GATING
352 /*
353 * The EC processor(CPU) cannot be in the k_cpu_idle() during
354 * the transactions with the CQ mode(DMA mode). Otherwise,
355 * the EC processor would be clock gated.
356 */
357 if (cpu_idle_not_allowed()) {
358 /* Restore global interrupt lockout state */
359 irq_unlock(MSTATUS_IEN);
360 } else
361 #endif
362 {
363 riscv_idle(CHIP_PLL_DOZE, MSTATUS_IEN);
364 }
365 }
366
arch_cpu_atomic_idle(unsigned int key)367 void arch_cpu_atomic_idle(unsigned int key)
368 {
369 riscv_idle(CHIP_PLL_DOZE, key);
370 }
371
ite_it8xxx2_init(void)372 static int ite_it8xxx2_init(void)
373 {
374 struct gpio_it8xxx2_regs *const gpio_regs = GPIO_IT8XXX2_REG_BASE;
375 struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
376
377 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usb0), disabled)
378 struct usb_it82xx2_regs *const usb_regs = USB_IT82XX2_REGS_BASE;
379
380 usb_regs->port0_misc_control &= ~PULL_DOWN_EN;
381 usb_regs->port1_misc_control &= ~PULL_DOWN_EN;
382 #endif
383
384 /*
385 * bit7: wake up CPU if it is in low power mode and
386 * an interrupt is pending.
387 */
388 gctrl_regs->GCTRL_WMCR |= BIT(7);
389
390 /*
391 * Disable USB debug at default, in order to prevent SoC
392 * from entering debug mode when there is signal toggling on GPH5/GPH6.
393 */
394 gctrl_regs->GCTRL_MCCR &= ~IT8XXX2_GCTRL_USB_DEBUG_EN;
395
396 /*
397 * Disable this feature that can detect pre-define hardware
398 * target A through I2C0. This is for debugging use, so it
399 * can be disabled to avoid illegal access.
400 */
401 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
402 IT8XXX2_SMB_SFFCTL &= ~IT8XXX2_SMB_HSAPE;
403 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2
404 IT8XXX2_SMB_SCLKTS_BRGS &= ~IT8XXX2_SMB_PREDEN;
405 /*
406 * Setting this bit will disable EGAD pin output driving to avoid
407 * leakage when GPIO E1/E2 on it82002 are set to alternate function.
408 */
409 IT8XXX2_EGPIO_EGCR |= IT8XXX2_EGPIO_EEPODD;
410 #endif
411
412 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart1))
413 /* UART1 board init */
414 /* bit2: clocks to UART1 modules are not gated. */
415 IT8XXX2_ECPM_CGCTRL3R &= ~BIT(2);
416 IT8XXX2_ECPM_AUTOCG &= ~BIT(6);
417
418 /* bit3: UART1 belongs to the EC side. */
419 gctrl_regs->GCTRL_RSTDMMC |= IT8XXX2_GCTRL_UART1SD;
420 /* reset UART before config it */
421 gctrl_regs->GCTRL_RSTC4 = IT8XXX2_GCTRL_RUART1;
422
423 /* switch UART1 on without hardware flow control */
424 gpio_regs->GPIO_GCR1 |= IT8XXX2_GPIO_U1CTRL_SIN0_SOUT0_EN;
425
426 #endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart1)) */
427
428 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart2))
429 /* UART2 board init */
430 /* setting voltage 3.3v */
431 gpio_regs->GPIO_GCR21 &= ~(IT8XXX2_GPIO_GPH1VS | IT8XXX2_GPIO_GPH2VS);
432 /* bit2: clocks to UART2 modules are not gated. */
433 IT8XXX2_ECPM_CGCTRL3R &= ~BIT(2);
434 IT8XXX2_ECPM_AUTOCG &= ~BIT(5);
435
436 /* bit3: UART2 belongs to the EC side. */
437 gctrl_regs->GCTRL_RSTDMMC |= IT8XXX2_GCTRL_UART2SD;
438 /* reset UART before config it */
439 gctrl_regs->GCTRL_RSTC4 = IT8XXX2_GCTRL_RUART2;
440
441 /* switch UART2 on without hardware flow control */
442 gpio_regs->GPIO_GCR1 |= IT8XXX2_GPIO_U2CTRL_SIN1_SOUT1_EN;
443
444 #endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart2)) */
445
446 #if (SOC_USBPD_ITE_PHY_PORT_COUNT > 0)
447 int port;
448
449 /*
450 * To prevent cc pins leakage, we disable board not active ITE
451 * TCPC port cc modules, then cc pins can be used as gpio if needed.
452 */
453 for (port = SOC_USBPD_ITE_ACTIVE_PORT_COUNT;
454 port < SOC_USBPD_ITE_PHY_PORT_COUNT; port++) {
455 struct usbpd_it8xxx2_regs *base;
456
457 if (port == 0) {
458 base = (struct usbpd_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(usbpd0));
459 } else if (port == 1) {
460 base = (struct usbpd_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(usbpd1));
461 } else {
462 /* Currently all ITE embedded pd chip support max two ports */
463 break;
464 }
465
466 /* Power down all CC, and disable CC voltage detector */
467 base->CCGCR |= (IT8XXX2_USBPD_DISABLE_CC |
468 IT8XXX2_USBPD_DISABLE_CC_VOL_DETECTOR);
469 /*
470 * Disconnect CC analog module (ex.UP/RD/DET/TX/RX), and
471 * disconnect CC 5.1K to GND
472 */
473 base->CCCSR |= (IT8XXX2_USBPD_CC2_DISCONNECT |
474 IT8XXX2_USBPD_CC2_DISCONNECT_5_1K_TO_GND |
475 IT8XXX2_USBPD_CC1_DISCONNECT |
476 IT8XXX2_USBPD_CC1_DISCONNECT_5_1K_TO_GND);
477 /* Disconnect CC 5V tolerant */
478 base->CCPSR |= (IT8XXX2_USBPD_DISCONNECT_POWER_CC2 |
479 IT8XXX2_USBPD_DISCONNECT_POWER_CC1);
480 /* Dis-connect 5.1K dead battery resistor to CC */
481 base->CCPSR |= (IT8XXX2_USBPD_DISCONNECT_5_1K_CC2_DB |
482 IT8XXX2_USBPD_DISCONNECT_5_1K_CC1_DB);
483 }
484 #endif /* (SOC_USBPD_ITE_PHY_PORT_COUNT > 0) */
485
486 return 0;
487 }
488 SYS_INIT(ite_it8xxx2_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
489
