4  * SPDX-License-Identifier: Apache-2.0
66 		while ((CCM->CDHIPR & ((1UL << busy_shift))) != 0UL) {  in clock_set_mux()
88 		while ((CCM->CDHIPR & ((uint32_t)(1UL << busy_shift))) != 0UL) {  in clock_set_div()
101 	/* Bypass PLL first */  in clock_init_usb1_pll()
102 	CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) |  in clock_init_usb1_pll()
103 		CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src);  in clock_init_usb1_pll()
105 	CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) |  in clock_init_usb1_pll()
108 		CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider);  in clock_init_usb1_pll()
110 	while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0UL) {  in clock_init_usb1_pll()
115 	CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK;  in clock_init_usb1_pll()
122 	while (!((FLEXSPI2->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) &&  in flexspi_enter_critical()
123 			(FLEXSPI2->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) {  in flexspi_enter_critical()
125 	FLEXSPI2->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;  in flexspi_enter_critical()
128 	CCM->CCGR7 &= (~CCM_CCGR7_CG1_MASK);  in flexspi_enter_critical()
133 	while (!((FLEXSPI->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) &&  in flexspi_enter_critical()
134 			(FLEXSPI->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) {  in flexspi_enter_critical()
136 	FLEXSPI->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;  in flexspi_enter_critical()
139 	CCM->CCGR6 &= (~CCM_CCGR6_CG5_MASK);  in flexspi_enter_critical()
146 	/* Enable clock gate of flexspi2. */  in flexspi_exit_critical()
147 	CCM->CCGR7 |= (CCM_CCGR7_CG1_MASK);  in flexspi_exit_critical()
149 	FLEXSPI2->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;  in flexspi_exit_critical()
150 	FLEXSPI2->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;  in flexspi_exit_critical()
151 	while (FLEXSPI2->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) {  in flexspi_exit_critical()
153 	while (!((FLEXSPI2->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) &&  in flexspi_exit_critical()
154 		(FLEXSPI2->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) {  in flexspi_exit_critical()
157 	/* Enable clock of flexspi. */  in flexspi_exit_critical()
158 	CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;  in flexspi_exit_critical()
160 	FLEXSPI->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;  in flexspi_exit_critical()
161 	FLEXSPI->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;  in flexspi_exit_critical()
162 	while (FLEXSPI->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) {  in flexspi_exit_critical()
164 	while (!((FLEXSPI->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) &&  in flexspi_exit_critical()
165 		(FLEXSPI->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) {  in flexspi_exit_critical()
168 	/* Invalidate I-cache after flexspi clock changed. */  in flexspi_exit_critical()
169 	if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) {  in flexspi_exit_critical()
178 	/* Set arm PLL div to divide by 2*/  in clock_full_power()
181 	/* Reinit arm pll based on saved configuration */  in clock_full_power()
186 	/* Reinit video pll */  in clock_full_power()
191 	/* Reinit enet pll */  in clock_full_power()
194 	/* Init SYS PLL */  in clock_full_power()
197 	/* Enable USB PLL PFD 1 2 3 */  in clock_full_power()
202 	/* Enable SYS PLL PFD0 1 2 3 */  in clock_full_power()
222 	/* Init USB1 PLL. This will disable the PLL3 bypass. */  in clock_full_power()
234 	/* MUX to ENET_500M (RT1010-1024) / ARM_PODF (RT1050-1064) */  in clock_full_power()
250 	/* Switch to 24MHz core clock, so ARM PLL can power down */  in clock_low_power()
257 	CCM_ANALOG->PLL_USB1_SET = CCM_ANALOG_PLL_USB1_BYPASS_MASK;  in clock_low_power()
258 	CCM_ANALOG->PLL_USB1_SET = CCM_ANALOG_PLL_USB1_ENABLE_MASK;  in clock_low_power()
259 	CCM_ANALOG->PFD_480_CLR = CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK;  in clock_low_power()
284 	/* Deinit ARM PLL */  in clock_low_power()
287 	/* Deinit SYS PLL */  in clock_low_power()
290 	/* Deinit SYS PLL PFD 0 1 2 3 */  in clock_low_power()
297 	/* Deinit USB1 PLL PFD 1 2 3 */  in clock_low_power()
302 	/* Deinit VIDEO PLL */  in clock_low_power()
305 	/* Deinit ENET PLL */  in clock_low_power()
314 	/* Enable RC OSC. It needs at least 4ms to be stable, so self tuning need to be enabled. */  in clock_lpm_init()
315 	XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK;  in clock_lpm_init()
317 	XTALOSC24M->OSC_CONFIG0 = XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(0x4) |  in clock_lpm_init()
322 	XTALOSC24M->OSC_CONFIG1 = XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(0x40) |  in clock_lpm_init()
327 	tmp_reg = XTALOSC24M->OSC_CONFIG0;  in clock_lpm_init()
331 	XTALOSC24M->OSC_CONFIG0 = tmp_reg;  in clock_lpm_init()
333 	tmp_reg = XTALOSC24M->OSC_CONFIG2;  in clock_lpm_init()
336 	XTALOSC24M->OSC_CONFIG2 = tmp_reg;  in clock_lpm_init()
338 	tmp_reg = XTALOSC24M->OSC_CONFIG1;  in clock_lpm_init()
339 	XTALOSC24M->OSC_CONFIG1 = tmp_reg;  in clock_lpm_init()
359 	/* Read configuration values for arm pll */  in imxrt_lpm_init()
360 	arm_pll_config.src = ((CCM_ANALOG->PLL_ARM &  in imxrt_lpm_init()
363 	arm_pll_config.loopDivider = ((CCM_ANALOG->PLL_ARM &  in imxrt_lpm_init()
367 	/* Read configuration values for sys pll */  in imxrt_lpm_init()
368 	sys_pll_config.src = ((CCM_ANALOG->PLL_SYS &  in imxrt_lpm_init()
371 	sys_pll_config.loopDivider = ((CCM_ANALOG->PLL_SYS &  in imxrt_lpm_init()
374 	sys_pll_config.numerator = CCM_ANALOG->PLL_SYS_NUM;  in imxrt_lpm_init()
375 	sys_pll_config.denominator = CCM_ANALOG->PLL_SYS_DENOM;  in imxrt_lpm_init()
376 	sys_pll_config.ss_step = ((CCM_ANALOG->PLL_SYS_SS &  in imxrt_lpm_init()
379 	sys_pll_config.ss_enable = ((CCM_ANALOG->PLL_SYS_SS &  in imxrt_lpm_init()
382 	sys_pll_config.ss_stop = ((CCM_ANALOG->PLL_SYS_SS &  in imxrt_lpm_init()
386 	/* Read configuration values for usb1 pll */  in imxrt_lpm_init()
387 	usb1_pll_config.src = ((CCM_ANALOG->PLL_USB1 &  in imxrt_lpm_init()
390 	usb1_pll_config.loopDivider = ((CCM_ANALOG->PLL_USB1 &  in imxrt_lpm_init()
394 	/* Read configuration values for video pll */  in imxrt_lpm_init()
395 	video_pll_config.src = ((CCM_ANALOG->PLL_VIDEO &  in imxrt_lpm_init()
398 	video_pll_config.loopDivider = ((CCM_ANALOG->PLL_VIDEO &  in imxrt_lpm_init()
401 	video_pll_config.numerator = CCM_ANALOG->PLL_VIDEO_NUM;  in imxrt_lpm_init()
402 	video_pll_config.denominator = CCM_ANALOG->PLL_VIDEO_DENOM;  in imxrt_lpm_init()
403 	switch ((CCM_ANALOG->PLL_VIDEO &  in imxrt_lpm_init()
410 			if (CCM_ANALOG->MISC2 & CCM_ANALOG_MISC2_VIDEO_DIV(3)) {  in imxrt_lpm_init()
417 			if (CCM_ANALOG->MISC2 & CCM_ANALOG_MISC2_VIDEO_DIV(3)) {  in imxrt_lpm_init()
428 	enet_pll_config.src = ((CCM_ANALOG->PLL_ENET &  in imxrt_lpm_init()
431 	enet_pll_config.loopDivider = ((CCM_ANALOG->PLL_ENET &  in imxrt_lpm_init()
434 	enet_pll_config.loopDivider1 = ((CCM_ANALOG->PLL_ENET &  in imxrt_lpm_init()
437 	enet_pll_config.enableClkOutput = (CCM_ANALOG->PLL_ENET &  in imxrt_lpm_init()
439 	enet_pll_config.enableClkOutput1 = (CCM_ANALOG->PLL_ENET &  in imxrt_lpm_init()
441 	enet_pll_config.enableClkOutput25M = (CCM_ANALOG->PLL_ENET &  in imxrt_lpm_init()
445 	/* Record all pll PFD values that we intend to disable in low power mode */  in imxrt_lpm_init()
446 	sys_pll_pfd0_frac = IMX_RT_SYS_PFD_FRAC(CCM_ANALOG->PFD_528, kCLOCK_Pfd0);  in imxrt_lpm_init()
447 	sys_pll_pfd1_frac = IMX_RT_SYS_PFD_FRAC(CCM_ANALOG->PFD_528, kCLOCK_Pfd1);  in imxrt_lpm_init()
448 	sys_pll_pfd2_frac = IMX_RT_SYS_PFD_FRAC(CCM_ANALOG->PFD_528, kCLOCK_Pfd2);  in imxrt_lpm_init()
449 	sys_pll_pfd3_frac = IMX_RT_SYS_PFD_FRAC(CCM_ANALOG->PFD_528, kCLOCK_Pfd3);  in imxrt_lpm_init()
451 	usb1_pll_pfd0_frac = IMX_RT_USB1_PFD_FRAC(CCM_ANALOG->PFD_480, kCLOCK_Pfd0);  in imxrt_lpm_init()
461 	usb1_pll_pfd1_frac = IMX_RT_USB1_PFD_FRAC(CCM_ANALOG->PFD_480, kCLOCK_Pfd1);  in imxrt_lpm_init()
462 	usb1_pll_pfd2_frac = IMX_RT_USB1_PFD_FRAC(CCM_ANALOG->PFD_480, kCLOCK_Pfd2);  in imxrt_lpm_init()
463 	usb1_pll_pfd3_frac = IMX_RT_USB1_PFD_FRAC(CCM_ANALOG->PFD_480, kCLOCK_Pfd3);  in imxrt_lpm_init()