1 /*
2  *
3  * Copyright (c) 2018 Ilya Tagunov
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 
9 #include <soc.h>
10 #include <stm32_ll_bus.h>
11 #include <stm32_ll_rcc.h>
12 #include <stm32_ll_pwr.h>
13 #include <stm32_ll_utils.h>
14 #include <zephyr/drivers/clock_control.h>
15 #include <zephyr/sys/util.h>
16 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
17 #include "clock_stm32_ll_common.h"
18 
19 #if defined(STM32_PLL_ENABLED)
20 
21 /* Macros to fill up multiplication and division factors values */
22 #define z_pll_mul(v) LL_RCC_PLL_MUL_ ## v
23 #define pll_mul(v) z_pll_mul(v)
24 
25 #define z_pll_div(v) LL_RCC_PLL_DIV_ ## v
26 #define pll_div(v) z_pll_div(v)
27 
28 /**
29  * @brief Return PLL source
30  */
31 __unused
get_pll_source(void)32 static uint32_t get_pll_source(void)
33 {
34 	/* Configure PLL source */
35 	if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
36 		return LL_RCC_PLLSOURCE_HSI;
37 	} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
38 		return LL_RCC_PLLSOURCE_HSE;
39 	}
40 
41 	__ASSERT(0, "Invalid source");
42 	return 0;
43 }
44 
45 /**
46  * @brief get the pll source frequency
47  */
48 __unused
get_pllsrc_frequency(void)49 uint32_t get_pllsrc_frequency(void)
50 {
51 	if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
52 		return STM32_HSI_FREQ;
53 	} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
54 		return STM32_HSE_FREQ;
55 	}
56 
57 	__ASSERT(0, "Invalid source");
58 	return 0;
59 }
60 
61 /**
62  * @brief Set up pll configuration
63  */
64 __unused
config_pll_sysclock(void)65 void config_pll_sysclock(void)
66 {
67 	LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
68 				    pll_mul(STM32_PLL_MULTIPLIER),
69 				    pll_div(STM32_PLL_DIVISOR));
70 }
71 
72 /**
73  * @brief Return pllout frequency
74  */
75 __unused
get_pllout_frequency(void)76 uint32_t get_pllout_frequency(void)
77 {
78 	return __LL_RCC_CALC_PLLCLK_FREQ(get_pllsrc_frequency(),
79 					 pll_mul(STM32_PLL_MULTIPLIER),
80 					 pll_div(STM32_PLL_DIVISOR));
81 }
82 
83 #endif /* defined(STM32_PLL_ENABLED) */
84 
85 /**
86  * @brief Set up voltage regulator voltage
87  */
config_regulator_voltage(uint32_t hclk_freq)88 void config_regulator_voltage(uint32_t hclk_freq)
89 {
90 	if (hclk_freq <= MHZ(4.2)) {
91 		LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE3);
92 	} else if (hclk_freq <= MHZ(16)) {
93 		LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
94 	} else {
95 		LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
96 	}
97 	while (LL_PWR_IsActiveFlag_VOS() == 1) {
98 	}
99 }
100 
101 /**
102  * @brief Activate default clocks
103  */
config_enable_default_clocks(void)104 void config_enable_default_clocks(void)
105 {
106 #if defined(CONFIG_EXTI_STM32) || defined(CONFIG_USB_DC_STM32) || \
107 	(defined(CONFIG_SOC_SERIES_STM32L0X) &&			  \
108 	 defined(CONFIG_ENTROPY_STM32_RNG))
109 	/* Enable System Configuration Controller clock. */
110 	LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
111 #endif
112 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
113 }
114