Lines Matching +full:pll +full:- +full:enable

4  * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
17 /* OSC/PLL is already initialized by ROM and Cortex-A53 (u-boot) */
27 	 * The M4 core is running at domain 1, enable clock gate for  in SOC_RdcInit()
39 	 * The M4 core is running at domain 1, enable the PLL clock sources  in SOC_RdcInit()
42 	/* Enable SysPLL1 to Domain 1 */  in SOC_RdcInit()
44 	/* Enable SysPLL2 to Domain 1 */  in SOC_RdcInit()
46 	/* Enable SysPLL3 to Domain 1 */  in SOC_RdcInit()
48 	/* Enable AudioPLL1 to Domain 1 */  in SOC_RdcInit()
50 	/* Enable AudioPLL2 to Domain 1 */  in SOC_RdcInit()
52 	/* Enable VideoPLL1 to Domain 1 */  in SOC_RdcInit()
58 	.refSel  = kANALOG_PllRefOsc24M, /* PLL reference OSC24M */
67 	.refSel  = kANALOG_PllRefOsc24M, /* PLL reference OSC24M */
94 	/* Switch cortex-m4 to SYSTEM PLL1 */  in SOC_ClockInit()
156 	/* Enable RDC clock */  in SOC_ClockInit()
160 	 * The purpose to enable the following modules clock is to make  in SOC_ClockInit()