7  * SPDX-License-Identifier: Apache-2.0
48 /** @brief returns the pll source frequency of given pll_id */
66 	__ASSERT(0, "No PLL Source configured");  in get_pllsrc_frequency()
144 	return -ENOTSUP;  in enabled_clock()
155 	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {  in stm32_clock_control_on()
157 		return -ENOTSUP;  in stm32_clock_control_on()
160 	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,  in stm32_clock_control_on()
161 		     pclken->enr);  in stm32_clock_control_on()
163 	temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);  in stm32_clock_control_on()
176 	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {  in stm32_clock_control_off()
178 		return -ENOTSUP;  in stm32_clock_control_off()
181 	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,  in stm32_clock_control_off()
182 		       pclken->enr);  in stm32_clock_control_off()
197 	err = enabled_clock(pclken->bus);  in stm32_clock_control_configure()
203 	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),  in stm32_clock_control_configure()
204 		     STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));  in stm32_clock_control_configure()
228 	switch (pclken->bus) {  in stm32_clock_control_get_subsys_rate()
342 		return -ENOTSUP;  in stm32_clock_control_get_subsys_rate()
345 	if (pclken->div) {  in stm32_clock_control_get_subsys_rate()
346 		*rate /= (pclken->div + 1);  in stm32_clock_control_get_subsys_rate()
375 		return -ERANGE;  in get_vco_input_range()
410 	/* Enable HSI if not enabled */  in clock_switch_to_hsi()
412 		/* Enable HSI */  in clock_switch_to_hsi()
439 	 * Switch to HSI and disable the PLL before configuration.  in set_up_plls()
441 	 * case we're currently running from the PLL we're about to  in set_up_plls()
450 	/* Configure PLL source : Can be HSE, HSI, MSIS */  in set_up_plls()
452 		/* Main PLL configuration and activation */  in set_up_plls()
455 		/* Main PLL configuration and activation */  in set_up_plls()
458 		/* Main PLL configuration and activation */  in set_up_plls()
461 		return -ENOTSUP;  in set_up_plls()
473 	/* Set VCO Input before enabling the PLL, depends on the freq of the PLL1 */  in set_up_plls()
475 	/* Select VCO freq range before enabling the PLL, depends on the freq of the PLL1 */  in set_up_plls()
501 	/* Init PLL source to None */  in set_up_plls()
514 		return -ENOTSUP;  in set_up_plls()
526 	/* Set VCO Input before enabling the PLL, depends on the freq of the PLL2 */  in set_up_plls()
528 	/* Select VCO freq range before enabling the PLL, depends on the freq of the PLL2 */  in set_up_plls()
568 		return -ENOTSUP;  in set_up_plls()
580 	/* Set VCO Input before enabling the PLL, depends on the freq of the PLL3 */  in set_up_plls()
582 	/* Select VCO freq range before enabling the PLL, depends on the freq of the PLL3 */  in set_up_plls()
620 		/* Check if need to enable HSE bypass feature or not */  in set_up_fixed_clock_sources()
627 		/* Enable HSE */  in set_up_fixed_clock_sources()
640 		/* Enable HSI if not enabled */  in set_up_fixed_clock_sources()
642 			/* Enable HSI */  in set_up_fixed_clock_sources()
654 			/* Enable write access to Backup domain */  in set_up_fixed_clock_sources()
669 		/* Enable LSE Oscillator */  in set_up_fixed_clock_sources()
685 		/* Enable CSI */  in set_up_fixed_clock_sources()
694 		/* Enable LSI oscillator */  in set_up_fixed_clock_sources()
763 		return -ENOTSUP;  in stm32_clock_control_init()