| /Zephyr-latest/dts/bindings/gpio/ |
| D | renesas,ra-gpio-ioport.yaml | 18 vbatts-pins:
30 port-irq0-pins:
32 description: Pins allow to assign port-irq0
34 port-irq1-pins:
36 description: Pins allow to assign port-irq1
38 port-irq2-pins:
40 description: Pins allow to assign port-irq2
42 port-irq3-pins:
44 description: Pins allow to assign port-irq3
46 port-irq4-pins:
[all …]
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| D | xlnx,ps-gpio.yaml | 10 ZynqMP (UltraScale) SoCs. It interfaces both I/O pins of the SoC,
11 which can be mapped in the system design tools (MIO pins), or SoC-
13 logic part of the SoC (EMIO pins).
16 of available GPIO pins differs between the two SoC families:
19 * Bank 0: MIO pins [31:00]
20 * Bank 1: MIO pins [53:32] (total: 54 MIO pins)
21 * Bank 2: EMIO pins [31:00]
22 * Bank 3: EMIO pins [63:32] (total: 64 EMIO pins)
25 * Bank 0: MIO pins [25:00]
26 * Bank 1: MIO pins [51:26]
[all …]
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| D | sparkfun,micromod-gpio.yaml | 5 GPIO pins exposed on micromod headers.
7 The micromod standard leverages the M.2 connector with 76 pins for
12 * An 6-pin Power Supply header. No pins on this header are exposed
14 * Reset, Boot pins and SWD pins not exposed by this binding.
15 * 2 UART buses. First with RTS and CTS pins, while the 2nd with only
16 RX and TX pins. Neither of them are exposed by this binding.
22 * 2 analog pins (A0 and A1).
23 * 2 digital pins (D0 and D1).
24 * 12 General purpose pins (G0 - G11).
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| D | particle-gen3-header.yaml | 5 GPIO pins exposed on Particle Gen3 (Feather) headers.
11 * A 12-pin header on the right. 9 pins on this header are exposed
13 * A 16-pin header. 13 pins on this header are exposed by this
16 This binding provides a nexus mapping for 22 pins where parent pins
17 0 through 8 correspond to the pins on the 12-pin header, starting
18 from the bottom; and pins 9 through 21 correspond to pins on the
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| D | adafruit-feather-header.yaml | 5 GPIO pins exposed on Adafruit Feather headers.
10 * A 16-pin header. 12 pins on this header are exposed
12 * A 12-pin header. 9 pins on this header are exposed
15 This binding provides a nexus mapping for 21 pins where parent pins 0
16 through 5 correspond to A0 through A5, and parent pins 6 through 20
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| /Zephyr-latest/tests/drivers/pinctrl/nrf/src/ |
| D | main.c | 27 zassert_equal(NRF_GET_FUN(scfg->pins[0]), NRF_FUN_UART_TX); in ZTEST()
28 zassert_equal(NRF_GET_LP(scfg->pins[0]), NRF_LP_DISABLE); in ZTEST()
29 zassert_equal(NRF_GET_DRIVE(scfg->pins[0]), NRF_DRIVE_S0S1); in ZTEST()
30 zassert_equal(NRF_GET_PULL(scfg->pins[0]), NRF_PULL_NONE); in ZTEST()
31 zassert_equal(NRF_GET_PIN(scfg->pins[0]), 1U); in ZTEST()
33 zassert_equal(NRF_GET_FUN(scfg->pins[1]), NRF_FUN_UART_RTS); in ZTEST()
34 zassert_equal(NRF_GET_LP(scfg->pins[1]), NRF_LP_DISABLE); in ZTEST()
35 zassert_equal(NRF_GET_DRIVE(scfg->pins[1]), NRF_DRIVE_S0S1); in ZTEST()
36 zassert_equal(NRF_GET_PULL(scfg->pins[1]), NRF_PULL_NONE); in ZTEST()
37 zassert_equal(NRF_GET_PIN(scfg->pins[1]), 2U); in ZTEST()
[all …]
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_silabs_dbus.c | 16 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) in pinctrl_configure_pins() argument
24 if (pins[i].en_bit == SILABS_PINCTRL_ANALOG) { in pinctrl_configure_pins()
26 (pins[i].base_offset * sizeof(mem_addr_t)); in pinctrl_configure_pins()
27 sys_write32(FIELD_PREP(ABUS_MASK(pins[i].mode), pins[i].route_offset), in pinctrl_configure_pins()
33 GPIO_PinModeSet(pins[i].port, pins[i].pin, pins[i].mode, pins[i].dout); in pinctrl_configure_pins()
37 (pins[i].base_offset * sizeof(mem_addr_t)); in pinctrl_configure_pins()
38 route_reg = enable_reg + (pins[i].route_offset * sizeof(mem_addr_t)); in pinctrl_configure_pins()
40 sys_write32(pins[i].port | FIELD_PREP(PIN_MASK, pins[i].pin), route_reg); in pinctrl_configure_pins()
42 if (pins[i].en_bit != SILABS_PINCTRL_UNUSED) { in pinctrl_configure_pins()
43 if (pins[i].mode == gpioModeDisabled) { in pinctrl_configure_pins()
[all …]
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| D | pinctrl_wch_afio.c | 18 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) in pinctrl_configure_pins() argument
22 for (i = 0; i < pin_cnt; i++, pins++) { in pinctrl_configure_pins()
23 uint8_t port = (pins->config >> CH32V003_PINCTRL_PORT_SHIFT) & 0x03; in pinctrl_configure_pins()
24 uint8_t pin = (pins->config >> CH32V003_PINCTRL_PIN_SHIFT) & 0x0F; in pinctrl_configure_pins()
25 uint8_t bit0 = (pins->config >> CH32V003_PINCTRL_RM_BASE_SHIFT) & 0x1F; in pinctrl_configure_pins()
26 uint8_t remap = (pins->config >> CH32V003_PINCTRL_RM_SHIFT) & 0x3; in pinctrl_configure_pins()
35 if (pins->output_high || pins->output_low) { in pinctrl_configure_pins()
36 cfg |= (pins->slew_rate + 1); in pinctrl_configure_pins()
37 if (pins->drive_open_drain) { in pinctrl_configure_pins()
43 if (pins->bias_pull_up || pins->bias_pull_down) { in pinctrl_configure_pins()
[all …]
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| D | pinctrl_wch_20x_30x_afio.c | 22 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) in pinctrl_configure_pins() argument
26 for (i = 0; i < pin_cnt; i++, pins++) { in pinctrl_configure_pins()
27 uint8_t port = FIELD_GET(CH32V20X_V30X_PINCTRL_PORT_MASK, pins->config); in pinctrl_configure_pins()
28 uint8_t pin = FIELD_GET(CH32V20X_V30X_PINCTRL_PIN_MASK, pins->config); in pinctrl_configure_pins()
29 uint8_t bit0 = FIELD_GET(CH32V20X_V30X_PINCTRL_RM_BASE_MASK, pins->config); in pinctrl_configure_pins()
30 uint8_t pcfr_id = FIELD_GET(CH32V20X_V30X_PINCTRL_PCFR_ID_MASK, pins->config); in pinctrl_configure_pins()
31 uint8_t remap = FIELD_GET(CH32V20X_V30X_PINCTRL_RM_MASK, pins->config); in pinctrl_configure_pins()
36 if (pins->output_high || pins->output_low) { in pinctrl_configure_pins()
37 cfg |= (pins->slew_rate + 1); in pinctrl_configure_pins()
38 if (pins->drive_open_drain) { in pinctrl_configure_pins()
[all …]
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| D | pinctrl_imx.c | 11 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, in pinctrl_configure_pins() argument
14 /* configure all pins */ in pinctrl_configure_pins()
16 uint32_t mux_register = pins[i].pinmux.mux_register; in pinctrl_configure_pins()
17 uint32_t mux_mode = pins[i].pinmux.mux_mode; in pinctrl_configure_pins()
18 uint32_t input_register = pins[i].pinmux.input_register; in pinctrl_configure_pins()
19 uint32_t input_daisy = pins[i].pinmux.input_daisy; in pinctrl_configure_pins()
20 uint32_t config_register = pins[i].pinmux.config_register; in pinctrl_configure_pins()
21 uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags; in pinctrl_configure_pins()
24 (volatile uint32_t *)((uintptr_t)pins[i].pinmux.gpr_register); in pinctrl_configure_pins()
27 if (pins[i].pinmux.gpr_val) { in pinctrl_configure_pins()
[all …]
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| /Zephyr-latest/dts/arm/renesas/ra/ra8/ |
| D | r7fa8m1xh.dtsi | 282 port-irq6-pins = <0>;
283 port-irq7-pins = <1>;
284 port-irq8-pins = <2>;
285 port-irq9-pins = <4>;
286 port-irq10-pins = <5>;
287 port-irq11-pins = <6>;
288 port-irq12-pins = <8>;
289 port-irq13-pins = <9 15>;
290 port-irq14-pins = <10>;
298 port-irq0-pins = <5>;
[all …]
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| D | r7fa8t1xh.dtsi | 263 port-irq6-pins = <0>;
264 port-irq7-pins = <1>;
265 port-irq8-pins = <2>;
266 port-irq9-pins = <4>;
267 port-irq10-pins = <5>;
268 port-irq11-pins = <6>;
269 port-irq12-pins = <8>;
270 port-irq13-pins = <9 15>;
271 port-irq14-pins = <10>;
279 port-irq0-pins = <5>;
[all …]
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| D | r7fa8d1xh.dtsi | 318 port-irq6-pins = <0>;
319 port-irq7-pins = <1>;
320 port-irq8-pins = <2>;
321 port-irq9-pins = <4>;
322 port-irq10-pins = <5>;
323 port-irq11-pins = <6>;
324 port-irq12-pins = <8>;
325 port-irq13-pins = <9 15>;
326 port-irq14-pins = <10>;
334 port-irq0-pins = <5>;
[all …]
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| /Zephyr-latest/dts/arm/renesas/ra/ra6/ |
| D | r7fa6m1ad3cfp.dtsi | 191 port-irq6-pins = <0>;
192 port-irq7-pins = <1>;
193 port-irq8-pins = <2>;
194 port-irq9-pins = <4>;
195 port-irq10-pins = <5>;
196 port-irq11-pins = <6>;
197 port-irq12-pins = <8>;
198 port-irq13-pins = <15>;
209 port-irq0-pins = <5>;
210 port-irq1-pins = <1 4>;
[all …]
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| D | r7fa6m2ax.dtsi | 223 port-irq6-pins = <0>;
224 port-irq7-pins = <1>;
225 port-irq8-pins = <2>;
226 port-irq9-pins = <4>;
227 port-irq10-pins = <5>;
228 port-irq11-pins = <6>;
229 port-irq12-pins = <8>;
230 port-irq13-pins = <9 15>;
241 port-irq0-pins = <5>;
242 port-irq1-pins = <1 4>;
[all …]
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| D | r7fa6m3ax.dtsi | 288 port-irq6-pins = <0>;
289 port-irq7-pins = <1>;
290 port-irq8-pins = <2>;
291 port-irq9-pins = <4>;
292 port-irq10-pins = <5>;
293 port-irq11-pins = <6>;
294 port-irq12-pins = <8>;
295 port-irq13-pins = <9 15>;
296 port-irq14-pins = <10>;
307 port-irq0-pins = <5>;
[all …]
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| D | r7fa6e10x.dtsi | 264 port-irq6-pins = <0>;
265 port-irq7-pins = <1>;
266 port-irq8-pins = <2>;
267 port-irq9-pins = <4>;
268 port-irq10-pins = <5>;
269 port-irq11-pins = <6>;
270 port-irq12-pins = <8>;
271 port-irq13-pins = <15>;
282 port-irq0-pins = <5>;
283 port-irq1-pins = <1 4>;
[all …]
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| D | r7fa6m5xh.dtsi | 466 port-irq6-pins = <0>;
467 port-irq7-pins = <1>;
468 port-irq8-pins = <2>;
469 port-irq9-pins = <4>;
470 port-irq10-pins = <5>;
471 port-irq11-pins = <6>;
472 port-irq12-pins = <8>;
473 port-irq13-pins = <9 15>;
474 port-irq14-pins = <10>;
485 port-irq0-pins = <5>;
[all …]
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| /Zephyr-latest/tests/drivers/pinctrl/api/src/ |
| D | main.c | 48 zassert_equal(TEST_GET_PIN(scfg->pins[0]), 0); in ZTEST()
49 zassert_equal(TEST_GET_PULL(scfg->pins[0]), TEST_PULL_UP); in ZTEST()
50 zassert_equal(TEST_GET_PIN(scfg->pins[1]), 1); in ZTEST()
51 zassert_equal(TEST_GET_PULL(scfg->pins[1]), TEST_PULL_DOWN); in ZTEST()
73 zassert_equal(TEST_GET_PIN(scfg->pins[0]), 10); in ZTEST()
74 zassert_equal(TEST_GET_PULL(scfg->pins[0]), TEST_PULL_DISABLE); in ZTEST()
75 zassert_equal(TEST_GET_PIN(scfg->pins[1]), 11); in ZTEST()
76 zassert_equal(TEST_GET_PULL(scfg->pins[1]), TEST_PULL_DISABLE); in ZTEST()
77 zassert_equal(TEST_GET_PIN(scfg->pins[2]), 12); in ZTEST()
78 zassert_equal(TEST_GET_PULL(scfg->pins[2]), TEST_PULL_DISABLE); in ZTEST()
[all …]
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| /Zephyr-latest/tests/drivers/pinctrl/api/ |
| D | app.overlay | 14 pins = <0>;
18 pins = <1>;
26 pins = <0>, <1>;
33 pins = <2>;
37 pins = <3>;
45 pins = <2>, <3>;
52 pins = <10>, <11>, <12>;
59 pins = <10>;
62 pins = <11>;
66 pins = <12>;
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| /Zephyr-latest/dts/arm/renesas/ra/ra4/ |
| D | r7fa4m2ax.dtsi | 285 port-irq6-pins = <0>;
286 port-irq7-pins = <1>;
287 port-irq8-pins = <2>;
288 port-irq9-pins = <4>;
289 port-irq10-pins = <5>;
290 port-irq11-pins = <6>;
291 port-irq12-pins = <8>;
292 port-irq13-pins = <15>;
303 port-irq0-pins = <5>;
304 port-irq1-pins = <1 4>;
[all …]
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| D | r7fa4m3ax.dtsi | 295 port-irq6-pins = <0>;
296 port-irq7-pins = <1>;
297 port-irq8-pins = <2>;
298 port-irq9-pins = <4>;
299 port-irq10-pins = <5>;
300 port-irq11-pins = <6>;
301 port-irq12-pins = <8>;
302 port-irq13-pins = <9 15>;
313 port-irq0-pins = <5>;
314 port-irq1-pins = <1 4>;
[all …]
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| D | r7fa4m1ax.dtsi | 250 port-irq2-pins = <2>;
251 port-irq3-pins = <4>;
252 port-irq6-pins = <0>;
253 port-irq7-pins = <1 15>;
254 port-irq10-pins = <5>;
255 port-irq15-pins = <11>;
266 port-irq0-pins = <5>;
267 port-irq1-pins = <1 4>;
268 port-irq2-pins = <0>;
269 port-irq3-pins = <10>;
[all …]
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| /Zephyr-latest/dts/bindings/test/ |
| D | vnd,pinctrl-test.yaml | 14 more groups, each defining the configuration for a set of pins.
19 pins sharing the same set of properties. Example:
25 /* configure pins 0 and 1 */
26 pins = <0>, <1>;
27 /* both pins 0 and 1 have pull-up enabled */
34 pins = <M>;
52 pins:
56 An array of pins sharing the same group properties. Each entry is a
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_sx1509b.c | 29 /* Number of pins supported by the device */
32 /* Max to select all pins supported on the device. */
38 /** Cache of the output configuration and data of the pins. */
146 /* Intensity register addresses for all 16 pins */
231 uint32_t pins) in sx1509_int_cb() argument
236 ARG_UNUSED(pins); in sx1509_int_cb()
244 struct sx1509b_pin_state *pins, bool data_first) in write_pin_state() argument
248 struct sx1509b_pin_state pins; in write_pin_state() member
253 pin_buf.pins.input_disable = sys_cpu_to_be16(pins->input_disable); in write_pin_state()
254 pin_buf.pins.long_slew = sys_cpu_to_be16(pins->long_slew); in write_pin_state()
[all …]
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