Lines Matching full:pins
10 ZynqMP (UltraScale) SoCs. It interfaces both I/O pins of the SoC,
11 which can be mapped in the system design tools (MIO pins), or SoC-
13 logic part of the SoC (EMIO pins).
16 of available GPIO pins differs between the two SoC families:
19 * Bank 0: MIO pins [31:00]
20 * Bank 1: MIO pins [53:32] (total: 54 MIO pins)
21 * Bank 2: EMIO pins [31:00]
22 * Bank 3: EMIO pins [63:32] (total: 64 EMIO pins)
25 * Bank 0: MIO pins [25:00]
26 * Bank 1: MIO pins [51:26]
27 * Bank 2: MIO pins [77:52] (total: 78 MIO pins, 26 per bank)
28 * Bank 3: EMIO pins [31:00]
29 * Bank 4: EMIO pins [63:32]
30 * Bank 5: EMIO pins [95:64] (total: 96 EMIO pins)
32 The controller is interrupt-capable. Certain pins both in the Zynq-