1 /*
2 * Copyright 2022, 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/arch/cpu.h>
8 #include <zephyr/init.h>
9 #include <zephyr/drivers/pinctrl.h>
10
pinctrl_configure_pins(const pinctrl_soc_pin_t * pins,uint8_t pin_cnt,uintptr_t reg)11 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
12 uintptr_t reg)
13 {
14 /* configure all pins */
15 for (uint8_t i = 0U; i < pin_cnt; i++) {
16 uint32_t mux_register = pins[i].pinmux.mux_register;
17 uint32_t mux_mode = pins[i].pinmux.mux_mode;
18 uint32_t input_register = pins[i].pinmux.input_register;
19 uint32_t input_daisy = pins[i].pinmux.input_daisy;
20 uint32_t config_register = pins[i].pinmux.config_register;
21 uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags;
22 #if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)
23 volatile uint32_t *gpr_register =
24 (volatile uint32_t *)((uintptr_t)pins[i].pinmux.gpr_register);
25 if (gpr_register) {
26 /* Set or clear specified GPR bit for this mux */
27 if (pins[i].pinmux.gpr_val) {
28 *gpr_register |=
29 (pins[i].pinmux.gpr_val << pins[i].pinmux.gpr_shift);
30 } else {
31 *gpr_register &= ~(0x1 << pins[i].pinmux.gpr_shift);
32 }
33 }
34 #endif
35
36 #ifdef CONFIG_SOC_MIMX9352
37 sys_write32(IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) |
38 IOMUXC1_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags)),
39 (mem_addr_t)mux_register);
40 if (input_register) {
41 sys_write32(IOMUXC1_SELECT_INPUT_DAISY(input_daisy),
42 (mem_addr_t)input_register);
43 }
44 if (config_register) {
45 sys_write32(pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT)),
46 (mem_addr_t)config_register);
47 }
48 #elif defined(CONFIG_SOC_MIMX8UD7)
49 if (mux_register == config_register) {
50 sys_write32(IOMUXC_PCR_MUX_MODE(mux_mode) |
51 pin_ctrl_flags, (mem_addr_t)mux_register);
52 } else {
53 sys_write32(IOMUXC_PCR_MUX_MODE(mux_mode),
54 (mem_addr_t)mux_register);
55
56 if (config_register) {
57 sys_write32(pin_ctrl_flags, (mem_addr_t)config_register);
58 }
59 }
60
61 if (input_register) {
62 sys_write32(IOMUXC_PSMI_SSS(input_daisy), (mem_addr_t)input_register);
63 }
64 #else
65 sys_write32(
66 IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) |
67 IOMUXC_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags)),
68 (mem_addr_t)mux_register);
69 if (input_register) {
70 sys_write32(IOMUXC_SELECT_INPUT_DAISY(input_daisy),
71 (mem_addr_t)input_register);
72 }
73 if (config_register) {
74 sys_write32(pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT)),
75 config_register);
76 }
77 #endif
78 }
79 return 0;
80 }
81
imx_pinctrl_init(void)82 static int imx_pinctrl_init(void)
83 {
84 #if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)
85 CLOCK_EnableClock(kCLOCK_Iomuxc);
86 #ifdef CONFIG_SOC_SERIES_IMXRT10XX
87 CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
88 CLOCK_EnableClock(kCLOCK_IomuxcGpr);
89 #elif defined(CONFIG_SOC_SERIES_IMXRT11XX)
90 CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr);
91 #endif /* CONFIG_SOC_SERIES_IMXRT10XX */
92 #elif defined(CONFIG_SOC_MIMX8MQ6)
93 CLOCK_EnableClock(kCLOCK_Iomux);
94 #endif /* CONFIG_SOC_SERIES_IMXRT10XX || CONFIG_SOC_SERIES_IMXRT11XX */
95 #if defined(CONFIG_SOC_SERIES_IMXRT118X)
96 CLOCK_EnableClock(kCLOCK_Iomuxc1);
97 CLOCK_EnableClock(kCLOCK_Iomuxc2);
98 #endif /* CONFIG_SOC_SERIES_IMXRT118X */
99 return 0;
100 }
101
102 SYS_INIT(imx_pinctrl_init, PRE_KERNEL_1, 0);
103
