1 /*
2 * Copyright (c) 2024 Silicon Laboratories Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/drivers/pinctrl.h>
8 #include <zephyr/arch/cpu.h>
9
10 #include <em_gpio.h>
11
12 #define DT_DRV_COMPAT silabs_dbus_pinctrl
13 #define PIN_MASK 0xF0000UL
14
pinctrl_configure_pins(const pinctrl_soc_pin_t * pins,uint8_t pin_cnt,uintptr_t reg)15 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
16 {
17 ARG_UNUSED(reg);
18
19 for (uint8_t i = 0U; i < pin_cnt; i++) {
20 mem_addr_t enable_reg, route_reg;
21
22 /* Configure GPIO */
23 GPIO_PinModeSet(pins[i].port, pins[i].pin, pins[i].mode, pins[i].dout);
24
25 /* Configure DBUS */
26 enable_reg = DT_INST_REG_ADDR(0) + (pins[i].base_offset * sizeof(mem_addr_t));
27 route_reg = enable_reg + (pins[i].route_offset * sizeof(mem_addr_t));
28
29 sys_write32(pins[i].port | FIELD_PREP(PIN_MASK, pins[i].pin), route_reg);
30
31 if (pins[i].en_bit != 0xFFU) {
32 sys_set_bit(enable_reg, pins[i].en_bit);
33 }
34 }
35
36 return 0;
37 }
38
