Home
last modified time | relevance | path

Searched full:factor (Results 1 – 25 of 233) sorted by relevance

12345678910

/Zephyr-latest/dts/arm/infineon/cat1a/
Dsystem_clocks.dtsi23 compatible = "fixed-factor-clock";
31 compatible = "fixed-factor-clock";
39 compatible = "fixed-factor-clock";
47 compatible = "fixed-factor-clock";
55 compatible = "fixed-factor-clock";
79 compatible = "fixed-factor-clock";
88 compatible = "fixed-factor-clock";
97 compatible = "fixed-factor-clock";
106 compatible = "fixed-factor-clock";
115 compatible = "fixed-factor-clock";
[all …]
/Zephyr-latest/dts/arm/infineon/cat1b/cyw20829/
Dsystem_clocks.dtsi38 compatible = "fixed-factor-clock";
46 compatible = "fixed-factor-clock";
54 compatible = "fixed-factor-clock";
62 compatible = "fixed-factor-clock";
70 compatible = "fixed-factor-clock";
79 compatible = "fixed-factor-clock";
88 compatible = "fixed-factor-clock";
97 compatible = "fixed-factor-clock";
/Zephyr-latest/dts/bindings/clock/
Dst,stm32f4-pll-clock.yaml8 input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock
37 Division factor for the PLL input clock
44 Main PLL multiplication factor for VCO
51 Main PLL division factor for PLLSAI2CLK
61 Main PLL (PLL) division factor for USB OTG FS, SDMMC and random number
68 Main PLL (PLL) division factor for I2S and DFSDM
Dst,stm32g0-pll-clock.yaml8 an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
37 Division factor for PLL input clock
44 Main PLL multiplication factor for VCO
50 PLL division factor for PLL P output
56 PLL division factor for PLL Q output
63 PLL division factor for PLLCLK (system clock)
Dst,stm32u0-pll-clock.yaml8 an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
37 Division factor M of the PLL
45 PLL frequency multiplication factor N
51 PLL VCO division factor P
57 PLL VCO division factor Q
64 PLL VCO division factor R
Dst,stm32h7-pll-clock.yaml11 an input frequency from 1 to 16 MHz. PLLM factor is used to set the input
40 Division factor for PLLx
48 Main PLL multiplication factor for VCOx
54 PLL division factor for pllx_p_ck
60 PLL division factor for pllx_q_ck
66 PLL division factor for pllx_r_ck
Dst,stm32wb-pll-clock.yaml11 an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
42 Main PLL division factor for PLL input clock
49 Main PLL multiplication factor for VCO
55 Main PLL division factor for PLLPCLK
61 Main PLL division factor for PLLQCLK
68 Main PLL division factor for PLLRCLK (system clock)
Dst,stm32l4-pll-clock.yaml11 an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
40 Division factor for the main PLL and audio PLLs (PLLSAI1 and PLLSAI2)
48 Main PLL multiplication factor for VCO
54 Main PLL division factor for PLLSAI3CLK
62 Main PLL division factor for PLL48M1CLK (48 MHz clock).
73 Main PLL division factor for PLLCLK (system clock)
Dst,stm32u5-pll-clock.yaml10 an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
51 PLLx multiplication factor for VCO
57 PLLx DIVP division factor
63 PLLx DIVQ division factor
70 PLLx DIVR division factor
Dst,stm32f7-pll-clock.yaml33 Division factor for the PLL input clock
40 PLL multiplication factor for VCO
47 PLL division factor for PLLCLK
57 PLL division factor for PLL48CK
Dst,stm32f2-pll-clock.yaml35 Division factor for the PLL input clock
42 PLL multiplication factor for VCO
49 PLL division factor for PLLCLK
59 PLL division factor for PLL48CK
Dst,stm32g4-pll-clock.yaml8 an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
37 Division factor for PLL input clock
44 Main PLL multiplication factor for VCO
50 Main PLL division factor for ADC
Dst,stm32wba-pll-clock.yaml10 an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
51 PLLx multiplication factor for VCO
57 PLLx DIVQ division factor
64 PLLx DIVR division factor
Dst,stm32f4-plli2s-clock.yaml7 Takes same input as Main PLL. PLLM factor and PLL source are common with Main PLL
28 PLLI2S multiplication factor for VCO
35 PLLI2S division factor for I2S Clocks
Dfixed-factor-clock.yaml4 description: Generic fixed factor clock provider
6 compatible: "fixed-factor-clock"
Dst,stm32h7rs-pll-clock.yaml10 an input frequency from 1 to 16 MHz. PLLM factor is used to set the input
33 PLL division factor for pllx_s_ck : valid for PLL1, 2, 3
39 PLL division factor for pllx_t_ck : valid for PLL2
Dnxp,kinetis-mcg.yaml22 Division factor is given as 2^fcrdiv.
29 Division factor is given as 2^lircdiv2.
/Zephyr-latest/dts/arm/silabs/
Defr32xg23.dtsi23 compatible = "fixed-factor-clock";
28 compatible = "fixed-factor-clock";
33 compatible = "fixed-factor-clock";
38 compatible = "fixed-factor-clock";
45 compatible = "fixed-factor-clock";
52 compatible = "fixed-factor-clock";
59 compatible = "fixed-factor-clock";
66 compatible = "fixed-factor-clock";
73 compatible = "fixed-factor-clock";
78 compatible = "fixed-factor-clock";
[all …]
Defr32mg24.dtsi23 compatible = "fixed-factor-clock";
28 compatible = "fixed-factor-clock";
33 compatible = "fixed-factor-clock";
38 compatible = "fixed-factor-clock";
45 compatible = "fixed-factor-clock";
52 compatible = "fixed-factor-clock";
59 compatible = "fixed-factor-clock";
66 compatible = "fixed-factor-clock";
73 compatible = "fixed-factor-clock";
78 compatible = "fixed-factor-clock";
[all …]
Defr32bg2x.dtsi23 compatible = "fixed-factor-clock";
28 compatible = "fixed-factor-clock";
35 compatible = "fixed-factor-clock";
42 compatible = "fixed-factor-clock";
49 compatible = "fixed-factor-clock";
56 compatible = "fixed-factor-clock";
63 compatible = "fixed-factor-clock";
68 compatible = "fixed-factor-clock";
73 compatible = "fixed-factor-clock";
78 compatible = "fixed-factor-clock";
[all …]
Defr32mg21.dtsi23 compatible = "fixed-factor-clock";
28 compatible = "fixed-factor-clock";
35 compatible = "fixed-factor-clock";
42 compatible = "fixed-factor-clock";
49 compatible = "fixed-factor-clock";
56 compatible = "fixed-factor-clock";
61 compatible = "fixed-factor-clock";
66 compatible = "fixed-factor-clock";
71 compatible = "fixed-factor-clock";
76 compatible = "fixed-factor-clock";
[all …]
/Zephyr-latest/drivers/audio/
Dmpxxdtyy.c54 uint16_t factor; in sw_filter_lib_init() local
58 /* calculate oversampling factor based on pdm clock */ in sw_filter_lib_init()
59 for (factor = 64U; factor <= 128U; factor += 64U) { in sw_filter_lib_init()
60 uint32_t pdm_bit_clk = (audio_freq * factor * in sw_filter_lib_init()
69 if (factor != 64U && factor != 128U) { in sw_filter_lib_init()
80 pdm_filter[i].Decimation = factor; in sw_filter_lib_init()
86 return factor; in sw_filter_lib_init()
124 * The number of PDM bytes per PCM sample is the decimation factor in sw_filter_lib_run()
Dmpxxdtyy-i2s.c101 uint16_t factor; in mpxxdtyy_i2s_configure() local
119 factor = sw_filter_lib_init(dev, cfg); in mpxxdtyy_i2s_configure()
120 if (factor == 0U) { in mpxxdtyy_i2s_configure()
132 i2s_cfg.frame_clk_freq = audio_freq * factor / chan_size; in mpxxdtyy_i2s_configure()
133 i2s_cfg.block_size = data->pcm_mem_size * (factor / chan_size); in mpxxdtyy_i2s_configure()
/Zephyr-latest/drivers/sensor/honeywell/mpr/
Dmpr_configuration.h61 /* psi to kPa conversion factor: 6.894757 * 10^6 */
65 /* kPa to kPa conversion factor: 1 * 10^6 */
69 /* bar to kPa conversion factor: 100 * 10^6 */
73 /* mbar to kPa conversion factor: 0.1 * 10^6 */
/Zephyr-latest/subsys/net/lib/coap/
DKconfig73 int "Random factor for ACK timeout described as percentage"
77 Factor described as percentage to extend CoAP ACK timeout. A value
78 of 150 means a factor of 1.50.
86 int "Retransmission backoff factor for ACK timeout described as percentage"
89 Factor described as percentage to extend CoAP ACK timeout for retransmissions.
90 A value of 200 means a factor of 2.0.

12345678910