1/*
2 * Copyright (c) 2021 Sateesh Kotapati
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv8-m.dtsi>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/i2c/i2c.h>
10#include <dt-bindings/pinctrl/gecko-pinctrl.h>
11#include <dt-bindings/adc/adc.h>
12#include <freq.h>
13
14/ {
15	chosen {
16		zephyr,flash-controller = &msc;
17		zephyr,entropy = &trng;
18	};
19
20	clocks {
21		sysclk: sysclk {
22			#clock-cells = <0>;
23			compatible = "fixed-factor-clock";
24			clocks = <&hfrcodpll>;
25		};
26		hclk: hclk {
27			#clock-cells = <0>;
28			compatible = "fixed-factor-clock";
29			clocks = <&sysclk>;
30			/* Divisors 1, 2, 4, 8, 16 allowed */
31			clock-div = <1>;
32		};
33		pclk: pclk {
34			#clock-cells = <0>;
35			compatible = "fixed-factor-clock";
36			clocks = <&hclk>;
37			/* Divisors 1, 2 allowed */
38			clock-div = <2>;
39		};
40		lspclk: lspclk {
41			#clock-cells = <0>;
42			compatible = "fixed-factor-clock";
43			clocks = <&pclk>;
44			/* Fixed divisor of 2 */
45			clock-div = <2>;
46		};
47		hclkdiv1024: hclkdiv1024 {
48			#clock-cells = <0>;
49			compatible = "fixed-factor-clock";
50			clocks = <&hclk>;
51			/* Fixed divisor of 1024 */
52			clock-div = <1024>;
53		};
54		traceclk: traceclk {
55			#clock-cells = <0>;
56			compatible = "fixed-factor-clock";
57			clocks = <&sysclk>;
58			/* Divisors 1, 2, 3, 4 allowed */
59			clock-div = <1>;
60		};
61		em01grpaclk: em01grpaclk {
62			#clock-cells = <0>;
63			compatible = "fixed-factor-clock";
64			clocks = <&hfrcodpll>;
65		};
66		em01grpbclk: em01grpbclk {
67			#clock-cells = <0>;
68			compatible = "fixed-factor-clock";
69			clocks = <&hfrcodpll>;
70		};
71		iadcclk: iadcclk {
72			#clock-cells = <0>;
73			compatible = "fixed-factor-clock";
74			clocks = <&em01grpaclk>;
75		};
76		em23grpaclk: em23grpaclk {
77			#clock-cells = <0>;
78			compatible = "fixed-factor-clock";
79			clocks = <&lfrco>;
80		};
81		em4grpaclk: em4grpaclk {
82			#clock-cells = <0>;
83			compatible = "fixed-factor-clock";
84			clocks = <&lfrco>;
85		};
86		rtccclk: rtccclk {
87			#clock-cells = <0>;
88			compatible = "fixed-factor-clock";
89			clocks = <&lfrco>;
90		};
91		wdog0clk: wdog0clk {
92			#clock-cells = <0>;
93			compatible = "fixed-factor-clock";
94			clocks = <&lfrco>;
95		};
96		systickclk: systickclk {
97			#clock-cells = <0>;
98			compatible = "fixed-factor-clock";
99			clocks = <&hclk>;
100		};
101	};
102
103	cpus {
104		#address-cells = <1>;
105		#size-cells = <0>;
106		cpu0: cpu@0 {
107			device_type = "cpu";
108			compatible = "arm,cortex-m33";
109			reg = <0>;
110			/*
111			 * EM1 is enabled by default because it is
112			 * unconditionally safe.
113			 *
114			 * EM2/3 can be enabled by the board code if proper
115			 * timing configuration is ensured:
116			 * - for EM2, EM3: BURTC used as sys_clock
117			 * - for EM3: BURTC clocked from ULFRCO
118			 * Using BURTC as sys_clock instead of SysTick
119			 * has implications on system performance. Read
120			 * KConfig documentation entry before enabling it.
121			 */
122			cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>;
123		};
124
125		power-states {
126			/*
127			 * EM1 is a basic "CPU WFI idle", all high-freq clocks remain
128			 * enabled.
129			 */
130			pstate_em1: em1 {
131				compatible = "zephyr,power-state";
132				power-state-name = "runtime-idle";
133				min-residency-us = <4>;
134				/* HFXO remains active */
135				exit-latency-us = <2>;
136			};
137
138			/*
139			 * EM2 is a deepsleep with HF clocks disabled by HW, voltages
140			 * scaled down, etc.
141			 */
142			pstate_em2: em2 {
143				compatible = "zephyr,power-state";
144				power-state-name = "suspend-to-idle";
145				min-residency-us = <260>;
146				exit-latency-us = <250>;
147			};
148
149			/*
150			 * EM3 seems to be exactly the same as EM2 except that
151			 * LFXO & LFRCO should be disabled, so you must use ULFRCO
152			 * as BURTC clock for the system to not lose track of time and
153			 * wake up.
154			 */
155			pstate_em3: em3 {
156				compatible = "zephyr,power-state";
157				power-state-name = "standby";
158				min-residency-us = <20000>;
159				exit-latency-us = <2000>;
160			};
161		};
162	};
163
164	sram0: memory@20000000 {
165		compatible = "mmio-sram";
166	};
167
168	soc {
169		cmu: clock@50008000 {
170			compatible = "silabs,series-clock";
171			reg = <0x50008000 0x4000>;
172			interrupt-names = "cmu";
173			status = "okay";
174			#clock-cells = <2>;
175		};
176
177		fsrco: fsrco@50018000 {
178			#clock-cells = <0>;
179			compatible = "fixed-clock";
180			reg = <0x50018000 0x4000>;
181			clock-frequency = <DT_FREQ_M(20)>;
182		};
183
184		clk_hfxo: hfxo: hfxo@5000c000 {
185			#clock-cells = <0>;
186			compatible = "silabs,hfxo";
187			reg = <0x5000c000 0x4000>;
188			clock-frequency = <DT_FREQ_K(38400)>;
189			ctune = <140>;
190			precision = <50>;
191			status = "disabled";
192		};
193
194		lfxo: lfxo@50020000 {
195			#clock-cells = <0>;
196			compatible = "silabs,series2-lfxo";
197			reg = <0x50020000 0x4000>;
198			clock-frequency = <32768>;
199			ctune = <63>;
200			precision = <50>;
201			timeout = <4096>;
202			status = "disabled";
203		};
204
205		hfrcodpll: hfrcodpll@50010000 {
206			#clock-cells = <0>;
207			compatible = "silabs,series2-hfrcodpll";
208			reg = <0x50010000 0x4000>;
209			clock-frequency = <DT_FREQ_M(19)>;
210		};
211
212		lfrco: lfrco@50024000 {
213			#clock-cells = <0>;
214			compatible = "silabs,series2-lfrco";
215			reg = <0x50024000 0x4000>;
216			clock-frequency = <32768>;
217		};
218
219		ulfrco: ulfrco@50028000 {
220			#clock-cells = <0>;
221			compatible = "fixed-clock";
222			reg = <0x50028000 0x4000>;
223			clock-frequency = <1000>;
224		};
225
226		msc: flash-controller@50030000 {
227			compatible = "silabs,gecko-flash-controller";
228			reg = <0x50030000 0xC69>;
229			interrupts = <49 0>;
230
231			#address-cells = <1>;
232			#size-cells = <1>;
233		};
234
235		usart0: usart@5005c000 {
236			compatible = "silabs,gecko-spi-usart";
237			reg = <0x5005C000 0x400>;
238			interrupt-names = "rx", "tx";
239			#address-cells = <1>;
240			#size-cells = <0>;
241			status = "disabled";
242		};
243
244		usart1: usart@50060000 {
245			compatible = "silabs,gecko-usart";
246			reg = <0x50060000 0x400>;
247			interrupt-names = "rx", "tx";
248			status = "disabled";
249		};
250
251		burtc0: burtc@50064000 {
252			compatible = "silabs,gecko-burtc";
253			reg = <0x50064000 0x3034>;
254			status = "disabled";
255		};
256
257		rtcc0: stimer0: rtcc@58000000 {
258			compatible = "silabs,gecko-stimer";
259			reg = <0x58000000 0x3054>;
260			clock-frequency = <32768>;
261			prescaler = <1>;
262			status = "disabled";
263		};
264
265		trng: trng@4c021000 {
266			compatible = "silabs,gecko-trng";
267			reg = <0x4C021000 0x1000>;
268			status = "disabled";
269			interrupts = <0x1 0x0>;
270		};
271
272		i2c0: i2c@5a010000 {
273			compatible = "silabs,gecko-i2c";
274			clock-frequency = <I2C_BITRATE_STANDARD>;
275			reg = <0x5a010000 0x3044>;
276			#address-cells = <1>;
277			#size-cells = <0>;
278			status = "disabled";
279		};
280
281		i2c1: i2c@50068000 {
282			compatible = "silabs,gecko-i2c";
283			clock-frequency = <I2C_BITRATE_STANDARD>;
284			reg = <0x50068000 0x3044>;
285			#address-cells = <1>;
286			#size-cells = <0>;
287			status = "disabled";
288		};
289
290		gpio: gpio@5003c000 {
291			compatible = "silabs,gecko-gpio";
292			reg = <0x5003C000 0x440>;
293			interrupt-names = "GPIO_EVEN", "GPIO_ODD";
294
295			ranges;
296			#address-cells = <1>;
297			#size-cells = <1>;
298
299			gpioa: gpio@5003c000 {
300				compatible = "silabs,gecko-gpio-port";
301				reg = <0x5003C000 0x30>;
302				gpio-controller;
303				#gpio-cells = <2>;
304				status = "disabled";
305			};
306
307			gpiob: gpio@5003c030 {
308				compatible = "silabs,gecko-gpio-port";
309				reg = <0x5003C030 0x30>;
310				gpio-controller;
311				#gpio-cells = <2>;
312				status = "disabled";
313			};
314
315			gpioc: gpio@5003c060 {
316				compatible = "silabs,gecko-gpio-port";
317				reg = <0x5003C060 0x30>;
318				gpio-controller;
319				#gpio-cells = <2>;
320				status = "disabled";
321			};
322
323			gpiod: gpio@5003c090 {
324				compatible = "silabs,gecko-gpio-port";
325				reg = <0x5003C090 0x30>;
326				gpio-controller;
327				#gpio-cells = <2>;
328				status = "disabled";
329			};
330
331			gpiof: gpio@5003c0c0 {
332				compatible = "silabs,gecko-gpio-port";
333				reg = <0x5003C0C0 0x30>;
334				gpio-controller;
335				#gpio-cells = <2>;
336				status = "disabled";
337			};
338
339		};
340
341		pinctrl: pin-controller@5003c440 {
342			compatible = "silabs,dbus-pinctrl";
343			reg = <0x5003c440 0xbc0>;
344		};
345
346		dma0: dma@40040000{
347			compatible = "silabs,ldma";
348			reg = <0x40040000 0x4000>;
349			#dma-cells = <3>;
350			dma_channels = <8>;
351			status = "disabled";
352		};
353
354		wdog0: wdog@4a018000 {
355			compatible = "silabs,gecko-wdog";
356			reg = <0x4A018000 0x3028>;
357			peripheral-id = <0>;
358			interrupts = <43 0>;
359			status = "disabled";
360		};
361
362		adc0: adc@5a004000 {
363			compatible = "silabs,gecko-iadc";
364			reg = <0x5a004000 0x4000>;
365			interrupts = <48 0>;
366			status = "disabled";
367			#io-channel-cells = <1>;
368		};
369
370		dcdc: dcdc@50094000 {
371			compatible = "silabs,series2-dcdc";
372			reg = <0x50094000 0x4000>;
373			status = "disabled";
374		};
375	};
376
377	bt_hci_silabs: bt_hci_silabs {
378		compatible = "silabs,bt-hci-efr32";
379		status = "disabled";
380	};
381};
382
383&nvic {
384	arm,num-irq-priority-bits = <4>;
385};
386