1/*
2 * Copyright (c) 2020 TriaGnoSys GmbH
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv8-m.dtsi>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/i2c/i2c.h>
10#include <dt-bindings/adc/adc.h>
11#include <dt-bindings/clock/silabs/xg24-clock.h>
12#include <freq.h>
13
14/ {
15	chosen {
16		zephyr,flash-controller = &msc;
17		zephyr,entropy = &se;
18	};
19
20	clocks {
21		hfxort: hfxort {
22			#clock-cells = <0>;
23			compatible = "fixed-factor-clock";
24			clocks = <&hfxo>;
25		};
26		hfrcodpllrt: hfrcodpllrt {
27			#clock-cells = <0>;
28			compatible = "fixed-factor-clock";
29			clocks = <&hfrcodpll>;
30		};
31		sysclk: sysclk {
32			#clock-cells = <0>;
33			compatible = "fixed-factor-clock";
34			clocks = <&hfrcodpll>;
35		};
36		hclk: hclk {
37			#clock-cells = <0>;
38			compatible = "fixed-factor-clock";
39			clocks = <&sysclk>;
40			/* Divider 1, 2, 4, 8, or 16 */
41			clock-div = <1>;
42		};
43		pclk: pclk {
44			#clock-cells = <0>;
45			compatible = "fixed-factor-clock";
46			clocks = <&hclk>;
47			/* Divider 1 or 2 */
48			clock-div = <2>;
49		};
50		lspclk: lspclk {
51			#clock-cells = <0>;
52			compatible = "fixed-factor-clock";
53			clocks = <&pclk>;
54			/* Fixed divider of 2 */
55			clock-div = <2>;
56		};
57		hclkdiv1024: hclkdiv1024 {
58			#clock-cells = <0>;
59			compatible = "fixed-factor-clock";
60			clocks = <&hclk>;
61			/* Fixed divider of 1024 */
62			clock-div = <1024>;
63		};
64		traceclk: traceclk {
65			#clock-cells = <0>;
66			compatible = "fixed-factor-clock";
67			clocks = <&sysclk>;
68			/* Divider 1, 2, 3 or 4 */
69			clock-div = <1>;
70		};
71		em01grpaclk: em01grpaclk {
72			#clock-cells = <0>;
73			compatible = "fixed-factor-clock";
74			clocks = <&hfrcodpll>;
75		};
76		em01grpcclk: em01grpcclk {
77			#clock-cells = <0>;
78			compatible = "fixed-factor-clock";
79			clocks = <&hfrcodpll>;
80		};
81		iadcclk: iadcclk {
82			#clock-cells = <0>;
83			compatible = "fixed-factor-clock";
84			clocks = <&em01grpaclk>;
85		};
86		em23grpaclk: em23grpaclk {
87			#clock-cells = <0>;
88			compatible = "fixed-factor-clock";
89			clocks = <&lfrco>;
90		};
91		em4grpaclk: em4grpaclk {
92			#clock-cells = <0>;
93			compatible = "fixed-factor-clock";
94			clocks = <&lfrco>;
95		};
96		sysrtcclk: sysrtcclk {
97			#clock-cells = <0>;
98			compatible = "fixed-factor-clock";
99			clocks = <&lfrco>;
100		};
101		wdog0clk: wdog0clk {
102			#clock-cells = <0>;
103			compatible = "fixed-factor-clock";
104			clocks = <&lfrco>;
105		};
106		wdog1clk: wdog1clk {
107			#clock-cells = <0>;
108			compatible = "fixed-factor-clock";
109			clocks = <&lfrco>;
110		};
111		pcnt0clk: pcnt0clk {
112			#clock-cells = <0>;
113			compatible = "fixed-factor-clock";
114			clocks = <&em23grpaclk>;
115		};
116		eusart0clk: eusart0clk {
117			#clock-cells = <0>;
118			compatible = "fixed-factor-clock";
119			clocks = <&em01grpcclk>;
120		};
121		systickclk: systickclk {
122			#clock-cells = <0>;
123			compatible = "fixed-factor-clock";
124			clocks = <&hclk>;
125		};
126		vdac0clk: vdac0clk {
127			#clock-cells = <0>;
128			compatible = "fixed-factor-clock";
129			clocks = <&em01grpaclk>;
130		};
131	};
132
133	cpus {
134		#address-cells = <1>;
135		#size-cells = <0>;
136
137		cpu0: cpu@0 {
138			device_type = "cpu";
139			compatible = "arm,cortex-m33";
140			reg = <0>;
141			cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>;
142		};
143
144		power-states {
145			/*
146			 * EM1 is a basic "CPU WFI idle", all high-freq clocks remain
147			 * enabled.
148			 */
149			pstate_em1: em1 {
150				compatible = "zephyr,power-state";
151				power-state-name = "runtime-idle";
152				min-residency-us = <4>;
153				/* HFXO remains active */
154				exit-latency-us = <2>;
155			};
156
157			/*
158			 * EM2 is a deepsleep with HF clocks disabled by HW, voltages
159			 * scaled down, etc.
160			 */
161			pstate_em2: em2 {
162				compatible = "zephyr,power-state";
163				power-state-name = "suspend-to-idle";
164				min-residency-us = <260>;
165				exit-latency-us = <250>;
166			};
167
168			/*
169			 * EM3 seems to be exactly the same as EM2 except that
170			 * LFXO & LFRCO should be disabled, so you must use ULFRCO
171			 * as BURTC clock for the system to not lose track of time and
172			 * wake up.
173			 */
174			pstate_em3: em3 {
175				compatible = "zephyr,power-state";
176				power-state-name = "standby";
177				min-residency-us = <20000>;
178				exit-latency-us = <2000>;
179			};
180		};
181	};
182
183	sram0: memory@20000000 {
184		device_type = "memory";
185		compatible = "mmio-sram";
186	};
187
188	soc {
189		cmu: clock@50008000 {
190			compatible = "silabs,series-clock";
191			reg = <0x50008000 0x4000>;
192			interrupts = <47 0>;
193			interrupt-names = "cmu";
194			status = "okay";
195			#clock-cells = <2>;
196		};
197
198		fsrco: fsrco@50018000 {
199			#clock-cells = <0>;
200			compatible = "fixed-clock";
201			reg = <0x50018000 0x4000>;
202			clock-frequency = <DT_FREQ_M(20)>;
203		};
204
205		clk_hfxo: hfxo: hfxo@5a004000 {
206			#clock-cells = <0>;
207			compatible = "silabs,hfxo";
208			reg = <0x5a004000 0x4000>;
209			interrupts = <44 0>;
210			interrupt-names = "hfxo";
211			clock-frequency = <DT_FREQ_M(39)>;
212			ctune = <140>;
213			precision = <50>;
214			status = "disabled";
215		};
216
217		lfxo: lfxo@50020000 {
218			#clock-cells = <0>;
219			compatible = "silabs,series2-lfxo";
220			reg = <0x50020000 0x4000>;
221			clock-frequency = <32768>;
222			ctune = <63>;
223			precision = <50>;
224			timeout = <4096>;
225			status = "disabled";
226		};
227
228		hfrcodpll: hfrcodpll@50010000 {
229			#clock-cells = <0>;
230			compatible = "silabs,series2-hfrcodpll";
231			reg = <0x50010000 0x4000>;
232			clock-frequency = <DT_FREQ_M(19)>;
233		};
234
235		hfrcoem23: hfrcoem23@5a000000 {
236			#clock-cells = <0>;
237			compatible = "silabs,series2-hfrcoem23";
238			reg = <0x5a000000 0x4000>;
239			clock-frequency = <DT_FREQ_M(19)>;
240		};
241
242		lfrco: lfrco@50024000 {
243			#clock-cells = <0>;
244			compatible = "silabs,series2-lfrco";
245			reg = <0x50024000 0x4000>;
246			clock-frequency = <32768>;
247		};
248
249		ulfrco: ulfrco@50028000 {
250			#clock-cells = <0>;
251			compatible = "fixed-clock";
252			reg = <0x50028000 0x4000>;
253			clock-frequency = <1000>;
254		};
255
256		clkin0: clkin0@5003c46c {
257			#clock-cells = <0>;
258			compatible = "fixed-clock";
259			reg = <0x5003c46c 0x4>;
260			clock-frequency = <DT_FREQ_M(38)>;
261		};
262
263		msc: flash-controller@50030000 {
264			compatible = "silabs,gecko-flash-controller";
265			reg = <0x50030000 0x3148>;
266			interrupts = <50 0>;
267
268			#address-cells = <1>;
269			#size-cells = <1>;
270
271			flash0: flash@8000000 {
272				compatible = "soc-nv-flash";
273				write-block-size = <4>;
274				erase-block-size = <8192>;
275			};
276		};
277
278		usart0: usart@5005c000 {
279			compatible = "silabs,gecko-usart";
280			reg = <0x5005C000 0x306c>;
281			interrupts = <9 0>, <10 0>;
282			interrupt-names = "rx", "tx";
283			peripheral-id = <0>;
284			clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
285			status = "disabled";
286		};
287
288		eusart0: eusart@5b010000 {
289			compatible = "silabs,gecko-spi-eusart";
290			reg = <0x5B010000 0x4000>;
291			interrupts = <11 0>, <12 0>;
292			interrupt-names = "rx", "tx";
293			clocks = <&cmu CLOCK_EUSART0 CLOCK_BRANCH_EUSART0CLK>;
294			status = "disabled";
295		};
296
297		eusart1: eusart@500a0000 {
298			compatible = "silabs,gecko-spi-eusart";
299			reg = <0x500A0000 0x4000>;
300			interrupts = <13 0>, <14 0>;
301			interrupt-names = "rx", "tx";
302			clocks = <&cmu CLOCK_EUSART1 CLOCK_BRANCH_EM01GRPCCLK>;
303			status = "disabled";
304		};
305
306		burtc0: burtc@50064000 {
307			compatible = "silabs,gecko-burtc";
308			reg = <0x50064000 0x3034>;
309			interrupts = <17 0>;
310			clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
311			status = "disabled";
312		};
313
314		se: semailbox@5c021000 {
315			compatible = "silabs,gecko-semailbox";
316			reg = <0x5c021000 0x1000>;
317			status = "disabled";
318			interrupts = <64 3>, <65 3>, <66 3>;
319			interrupt-names = "SETAMPERHOST", "SEMBRX", "SEMBTX";
320		};
321
322		i2c0: i2c@5b000000 {
323			compatible = "silabs,gecko-i2c";
324			clock-frequency = <I2C_BITRATE_STANDARD>;
325			#address-cells = <1>;
326			#size-cells = <0>;
327			reg = <0x5b000000 0x3044>;
328			interrupts = <27 0>;
329			clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
330			status = "disabled";
331		};
332
333		sysrtc0: stimer0: sysrtc@500a8000 {
334			compatible = "silabs,gecko-stimer";
335			reg = <0x500a8000 0x3054>;
336			interrupts = <67 0>, <68 0>;
337			interrupt-names = "sysrtc_app", "sysrtc_seq";
338			clock-frequency = <32768>;
339			prescaler = <1>;
340			clocks = <&cmu CLOCK_SYSRTC0 CLOCK_BRANCH_SYSRTCCLK>;
341			status = "disabled";
342		};
343
344		gpio: gpio@5003c000 {
345			compatible = "silabs,gecko-gpio";
346			reg = <0x5003c000 0x440>;
347			interrupts = <26 2>, <25 2>;
348			interrupt-names = "GPIO_EVEN", "GPIO_ODD";
349			clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
350
351			ranges;
352			#address-cells = <1>;
353			#size-cells = <1>;
354
355			gpioa: gpio@5003c030 {
356				compatible = "silabs,gecko-gpio-port";
357				reg = <0x5003c030 0x30>;
358				peripheral-id = <0>;
359				gpio-controller;
360				#gpio-cells = <2>;
361				status = "disabled";
362			};
363
364			gpiob: gpio@5003c060 {
365				compatible = "silabs,gecko-gpio-port";
366				reg = <0x5003c060 0x30>;
367				peripheral-id = <1>;
368				gpio-controller;
369				#gpio-cells = <2>;
370				status = "disabled";
371			};
372
373			gpioc: gpio@5003c090 {
374				compatible = "silabs,gecko-gpio-port";
375				reg = <0x5003c090 0x30>;
376				peripheral-id = <2>;
377				gpio-controller;
378				#gpio-cells = <2>;
379				status = "disabled";
380			};
381
382			gpiod: gpio@5003c0C0 {
383				compatible = "silabs,gecko-gpio-port";
384				reg = <0x5003c0C0 0x30>;
385				peripheral-id = <3>;
386				gpio-controller;
387				#gpio-cells = <2>;
388				status = "disabled";
389			};
390		};
391
392		pinctrl: pin-controller@5003c440 {
393			compatible = "silabs,dbus-pinctrl";
394			reg = <0x5003c440 0xbc0>;
395		};
396
397		dma0: dma@40040000 {
398			compatible = "silabs,ldma";
399			reg = <0x40040000 0x4000>;
400			interrupts = <21 0>;
401			#dma-cells = <3>;
402			dma_channels = <8>;
403			status = "disabled";
404		};
405
406		wdog0: wdog@5b004000 {
407			compatible = "silabs,gecko-wdog";
408			reg = <0x5b004000 0x2C>;
409			peripheral-id = <0>;
410			interrupts = <42 0>;
411			clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>;
412			status = "disabled";
413		};
414
415		wdog1: wdog@5b008000 {
416			compatible = "silabs,gecko-wdog";
417			reg = <0x5b008000 0x2C>;
418			peripheral-id = <1>;
419			interrupts = <43 0>;
420			clocks = <&cmu CLOCK_WDOG1 CLOCK_BRANCH_WDOG1CLK>;
421			status = "disabled";
422		};
423
424		adc0: adc@59004000 {
425			compatible = "silabs,gecko-iadc";
426			reg = <0x59004000 0x4000>;
427			interrupts = <49 0>;
428			clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
429			status = "disabled";
430			#io-channel-cells = <1>;
431		};
432
433		dcdc: dcdc@50094000 {
434			compatible = "silabs,series2-dcdc";
435			reg = <0x50094000 0x4000>;
436			interrupts = <53 0>;
437			status = "disabled";
438		};
439	};
440
441
442	bt_hci_silabs: bt_hci_silabs {
443		compatible = "silabs,bt-hci-efr32";
444		status = "disabled";
445	};
446};
447
448/ {
449	hwinfo: hwinfo {
450		compatible = "silabs,gecko-hwinfo";
451		status = "disabled";
452	};
453
454};
455
456&nvic {
457	arm,num-irq-priority-bits = <4>;
458};
459