Searched full:division (Results 1 – 25 of 114) sorted by relevance
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| /Zephyr-latest/dts/bindings/tcpc/ |
| D | st,stm32-ucpd.yaml | 35 Determines the division ratio of a kernel clock pre-scaler
44 Determines the division ratio of a ucpd_clk divider producing
46 The division ratio 15 is to apply for Tx clock at the USB PD 2.0
54 Determines the division ratio of a hbit_clk divider producing
62 Determines the division ratio of a ucpd_clk divider producing
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| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32u5-pll-clock.yaml | 57 PLLx DIVP division factor
63 PLLx DIVQ division factor
70 PLLx DIVR division factor
71 On PLL1, only division by 1 and even division values are allowed.
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| D | st,stm32f4-pll-clock.yaml | 37 Division factor for the PLL input clock
51 Main PLL division factor for PLLSAI2CLK
61 Main PLL (PLL) division factor for USB OTG FS, SDMMC and random number
68 Main PLL (PLL) division factor for I2S and DFSDM
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| D | st,stm32g0-pll-clock.yaml | 37 Division factor for PLL input clock
50 PLL division factor for PLL P output
56 PLL division factor for PLL Q output
63 PLL division factor for PLLCLK (system clock)
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| D | st,stm32u0-pll-clock.yaml | 37 Division factor M of the PLL
51 PLL VCO division factor P
57 PLL VCO division factor Q
64 PLL VCO division factor R
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| D | st,stm32h7-pll-clock.yaml | 40 Division factor for PLLx
54 PLL division factor for pllx_p_ck
60 PLL division factor for pllx_q_ck
66 PLL division factor for pllx_r_ck
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| D | st,stm32wb-pll-clock.yaml | 42 Main PLL division factor for PLL input clock
55 Main PLL division factor for PLLPCLK
61 Main PLL division factor for PLLQCLK
68 Main PLL division factor for PLLRCLK (system clock)
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| D | st,stm32l4-pll-clock.yaml | 40 Division factor for the main PLL and audio PLLs (PLLSAI1 and PLLSAI2)
54 Main PLL division factor for PLLSAI3CLK
62 Main PLL division factor for PLL48M1CLK (48 MHz clock).
73 Main PLL division factor for PLLCLK (system clock)
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| D | st,stm32f7-pll-clock.yaml | 33 Division factor for the PLL input clock
47 PLL division factor for PLLCLK
57 PLL division factor for PLL48CK
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| D | st,stm32f2-pll-clock.yaml | 35 Division factor for the PLL input clock
49 PLL division factor for PLLCLK
59 PLL division factor for PLL48CK
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| D | nxp,kinetis-mcg.yaml | 22 Division factor is given as 2^fcrdiv.
29 Division factor is given as 2^lircdiv2.
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| D | st,stm32f411-plli2s-clock.yaml | 25 Division factor for the PLL input clock
31 PLLI2S division factor for I2S Clocks to supply USB/SDIO/RNG
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| D | st,stm32g4-pll-clock.yaml | 37 Division factor for PLL input clock
50 Main PLL division factor for ADC
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| D | st,stm32h7rs-pll-clock.yaml | 33 PLL division factor for pllx_s_ck : valid for PLL1, 2, 3
39 PLL division factor for pllx_t_ck : valid for PLL2
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| D | st,stm32wba-pll-clock.yaml | 57 PLLx DIVQ division factor
64 PLLx DIVR division factor
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| /Zephyr-latest/soc/ite/ec/it8xxx2/ |
| D | __arithmetic.S | 34 /* signed 32 bit division. opcode of div a0,a0,a1 is 0x02b54533 */
37 /* unsigned 32 bit division. opcode of divu a0,a0,a1 is 0x02b55533 */
41 * This function return the remainder of the signed division.
47 * This function return the remainder of the unsigned division.
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| /Zephyr-latest/dts/bindings/timer/ |
| D | nuclei,systimer.yaml | 24 clk-divider specifies the division ratio to the CPU frequency that
38 The relationship with the frequency division ratio is as
47 Division ratio constants can be found in the
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| /Zephyr-latest/dts/bindings/mipi-dsi/ |
| D | st,stm32-mipi-dsi.yaml | 69 DSI host dedicated PLL loop division factor.
75 DSI host dedicated PLL input division factor.
81 DSI HOST dedicated PLL output division factor.
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| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.riscv_machine | 28 Specifies the division ratio of the system clock supplied to the Machine Timer.
37 The division ratio should define in devicetree,
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| /Zephyr-latest/drivers/sensor/st/vl53l1x/ |
| D | vl53l1_platform_user_defines.h | 26 * @brief customer supplied division operation - 64-bit unsigned
36 * @brief customer supplied division operation - 64-bit signed
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| /Zephyr-latest/dts/bindings/mmc/ |
| D | st,stm32-sdmmc.yaml | 46 Clock division factor for SDMMC. Typically the clock operates at 25MHz so
47 a division factor of 2 would be 25MHz / 2 = 12.5MHz.
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | infineon,cat1-pwm.yaml | 55 Causes integer division of (divider value + 1), or division by 1 to 256
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| /Zephyr-latest/dts/bindings/led/ |
| D | issi,is31fl3216a.yaml | 5 is31fl3216a LED driver for Lumissil Microsystems (a division of ISSI)
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| /Zephyr-latest/drivers/led/ |
| D | Kconfig.is31fl3194 | 10 Enable LED driver for Lumissil Microsystems (a division of ISSI)
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| D | Kconfig.is31fl3216a | 10 Enable LED driver for Lumissil Microsystems (a division of ISSI)
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