1# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
2# an affiliate of Cypress Semiconductor Corporation
3#
4# SPDX-License-Identifier: Apache-2.0
5
6description: Infineon Cat1 PWM
7
8compatible: "infineon,cat1-pwm"
9
10include: [pwm-controller.yaml, pinctrl-device.yaml]
11
12properties:
13  reg:
14    type: array
15    required: true
16
17  interrupts:
18    type: array
19    required: true
20
21  pinctrl-0:
22    description: |
23      PORT pin configuration for the PWM signal.
24      We expect that the phandles will reference pinctrl nodes. These
25      nodes will have a nodelabel that matches the Infineon SoC Pinctrl
26      defines and have following
27      format: p<port>_<pin>_<peripheral inst>_<signal>.
28
29      Examples:
30        pinctrl-0 = <&p1_1_pwm0_0>;
31    required: true
32
33  pinctrl-names:
34    required: true
35
36  resolution:
37    type: int
38
39  divider-type:
40    type: int
41    description: |
42      Specifies which type of divider to use.
43      Defined by cy_en_divider_types_t in cy_sysclk.h.
44    required: true
45
46  divider-sel:
47    type: int
48    description: |
49      Specifies which divider of the selected type to configure.
50    required: true
51
52  divider-val:
53    type: int
54    description: |
55      Causes integer division of (divider value + 1), or division by 1 to 256
56      (8-bit divider) or 1 to 65536 (16-bit divider).
57    required: true
58
59  "#pwm-cells":
60    const: 3
61    description: |
62      Number of items to expect in a PWM
63      - channel of the timer used for PWM (not used)
64      - period to set in ns
65      - flags: standard flags like PWM_POLARITY_NORMAL
66
67pwm-cells:
68  - channel
69  - period
70  - flags
71