Searched +full:clock +full:- +full:select (Results 1 – 25 of 529) sorted by relevance
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| /Zephyr-latest/soc/nxp/kinetis/k8x/ |
| D | Kconfig | 5 # SPDX-License-Identifier: Apache-2.0
8 select ARM
9 select CPU_CORTEX_M4
10 select CPU_CORTEX_M_HAS_DWT
11 select CPU_HAS_NXP_SYSMPU
12 select CPU_HAS_FPU
13 select CLOCK_CONTROL
14 select HAS_MCUX
15 select HAS_MCUX_ADC16
16 select HAS_MCUX_FTFX
[all …]
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| /Zephyr-latest/soc/nxp/imxrt/imxrt5xx/ |
| D | Kconfig | 3 # SPDX-License-Identifier: Apache-2.0
6 select CPU_CORTEX_M33
7 select CLOCK_CONTROL
8 select CPU_CORTEX_M_HAS_DWT
9 select ARM
10 select HAS_PM
11 select HAS_POWEROFF
12 select CPU_HAS_ARM_SAU
13 select CPU_HAS_ARM_MPU
14 select CPU_HAS_FPU
[all …]
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| /Zephyr-latest/soc/nordic/nrf52/ |
| D | Kconfig | 3 # Copyright (c) 2016-2023 Nordic Semiconductor ASA
4 # SPDX-License-Identifier: Apache-2.0
7 select ARM
8 select SOC_COMPATIBLE_NRF52X
9 select CPU_CORTEX_M4
10 select CPU_HAS_ARM_MPU
12 select HAS_NRFX
13 select HAS_NORDIC_DRIVERS
14 select HAS_NORDIC_RAM_CTRL
15 select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
[all …]
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| /Zephyr-latest/drivers/clock_control/ |
| D | Kconfig.nrf | 1 # Clock controller driver configuration options
4 # SPDX-License-Identifier: Apache-2.0
11 of the clock control driver.
14 bool "NRF Clock controller support"
17 select NRFX_CLOCK if !CLOCK_CONTROL_NRF_FORCE_ALT
18 select ONOFF
20 Enable support for the Nordic Semiconductor nRFxx series SoC clock
30 prompt "32KHz clock source"
37 select NRFX_CLOCK_LFXO_TWO_STAGE_ENABLED if (!SOC_SERIES_BSIM_NRFXX && \
47 select NRFX_CLOCK_LFXO_TWO_STAGE_ENABLED if !CLOCK_CONTROL_NRF_FORCE_ALT
[all …]
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| D | Kconfig.stm32 | 1 # STM32 MCU clock control driver config
5 # SPDX-License-Identifier: Apache-2.0
8 bool "STM32 Reset & Clock Control"
11 select USE_STM32_LL_UTILS
12 select USE_STM32_LL_RCC if (SOC_SERIES_STM32MP1X || SOC_SERIES_STM32H7X || \
14 select RUNTIME_NMI if ($(dt_nodelabel_enabled,clk_hse) && \
15 $(dt_nodelabel_has_prop,clk_hse,css-enabled))
17 Enable driver for Reset & Clock Control subsystem found
23 DT_STM32_HSE_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_HSE_CLOCK),clock-frequency)
26 int "HSE clock value"
[all …]
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| D | clock_control_lpc11u6x.h | 4 * SPDX-License-Identifier: Apache-2.0
70 volatile uint32_t sys_pll_clk_sel; /* System PLL clock source */
72 volatile uint32_t usb_pll_clk_sel; /* USB PLL clock source */
73 volatile uint32_t usb_pll_clk_uen; /* USB PLL clock source
77 volatile uint32_t main_clk_sel; /* Main clock select */
78 volatile uint32_t main_clk_uen; /* Main clock update */
79 volatile uint32_t sys_ahb_clk_div; /* System clock divider */
81 volatile uint32_t sys_ahb_clk_ctrl; /* System clock control */
83 volatile uint32_t ssp0_clk_div; /* SSP0 clock divider */
84 volatile uint32_t usart0_clk_div; /* USART0 clock divider */
[all …]
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| /Zephyr-latest/soc/nxp/lpc/lpc55xxx/ |
| D | Kconfig | 2 # SPDX-License-Identifier: Apache-2.0
5 select HAS_MCUX
6 select HAS_MCUX_FLEXCOMM
7 select HAS_MCUX_SYSCON
8 select HAS_MCUX_WWDT
9 select CPU_CORTEX_M_HAS_SYSTICK
10 select CPU_CORTEX_M_HAS_DWT
11 select SOC_RESET_HOOK
14 select CPU_CORTEX_M33
15 select CPU_HAS_ARM_SAU
[all …]
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| /Zephyr-latest/soc/nxp/imx/imx7d/ |
| D | soc.c | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
13 /* Initialize clock. */
16 /* OSC/PLL is already initialized by Cortex-A7 (u-boot) */ in SOC_ClockInit()
20 * Note : The WDOG clock Root is shared by all the 4 WDOGs, in SOC_ClockInit()
39 /* Enable clock gate for IP bridge and IO mux */ in SOC_ClockInit()
46 /* Enable clock gate for RDC */ in SOC_ClockInit()
62 /* Enable gpio clock gate */ in nxp_mcimx7_gpio_config()
69 /* Enable gpio clock gate */ in nxp_mcimx7_gpio_config()
76 /* Enable gpio clock gate */ in nxp_mcimx7_gpio_config()
[all …]
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| /Zephyr-latest/drivers/ethernet/nxp_enet/ |
| D | Kconfig | 3 # Copyright (c) 2016-2017 ARM Ltd
5 # SPDX-License-Identifier: Apache-2.0
17 select NOCACHE_MEMORY if HAS_MCUX_CACHE && CPU_HAS_DCACHE
18 select ARM_MPU if CPU_CORTEX_M7
19 select MDIO if DT_HAS_NXP_ENET_MDIO_ENABLED
20 select NET_POWER_MANAGEMENT if (PM_DEVICE && SOC_FAMILY_KINETIS)
21 select ETH_DSA_SUPPORT
22 select PINCTRL
28 select NOCACHE_MEMORY if HAS_MCUX_CACHE && CPU_HAS_DCACHE
29 select ARM_MPU if CPU_CORTEX_M7
[all …]
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| /Zephyr-latest/soc/ite/ec/it8xxx2/ |
| D | Kconfig | 2 # SPDX-License-Identifier: Apache-2.0
5 select CPU_HAS_FPU if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" || RISCV_ISA_EXT_M
6 select HAS_PM
7 select ARCH_HAS_CUSTOM_CPU_IDLE
8 select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
9 select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
14 select RISCV
15 select ATOMIC_OPERATIONS_BUILTIN
16 select RISCV_ISA_RV32I
17 select RISCV_ISA_EXT_ZICSR
[all …]
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| /Zephyr-latest/soc/nxp/kinetis/ke1xf/ |
| D | Kconfig | 5 # SPDX-License-Identifier: Apache-2.0
8 select ARM
9 select CPU_CORTEX_M4
10 select CPU_CORTEX_M_HAS_DWT
11 select CPU_HAS_NXP_SYSMPU
12 select CPU_HAS_FPU
13 select CLOCK_CONTROL
14 select HAS_MCUX
15 select HAS_MCUX_CACHE
16 select HAS_MCUX_FTFX
[all …]
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| /Zephyr-latest/drivers/dai/nxp/sai/ |
| D | Kconfig.sai | 2 # SPDX-License-Identifier: Apache-2.0
8 select PINCTRL
10 Select this to enable NXP SAI driver.
18 Select this if the SAI IP allows configuration
19 of the master clock. Master clock configuration
20 refers to enabling/disabling the master clock,
22 the master clock output.
35 Select this if your SAI ip version is affected by
|
| /Zephyr-latest/dts/bindings/adc/ |
| D | nxp,vf610-adc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,vf610-adc"
8 include: [adc-controller.yaml, "nxp,rdc-policy.yaml"]
17 clk-source:
21 Select adc clock source: 0 clock from IPG, 1 clock from IPG divided 2, 2 async clock
23 clk-divider:
27 Select clock divider: 0 clock divided by 1, 1 clock divided by 2, 2 clock divided by 4,
28 3 clock divided by 8
30 "#io-channel-cells":
33 io-channel-cells:
[all …]
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| /Zephyr-latest/dts/bindings/misc/ |
| D | renesas,ra-external-interrupt.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,ra-external-interrupt"
24 - "falling"
25 - "rising"
26 - "both-edges"
27 - "low-level"
29 Select the signal edge or state that triggers an interrupt
31 renesas,digital-filtering:
34 Select if data noise filter should be enabled.
36 renesas,sample-clock-div:
[all …]
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| /Zephyr-latest/soc/nxp/lpc/lpc54xxx/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
7 select ARM
8 select HAS_MCUX
9 select HAS_MCUX_FLEXCOMM
10 select HAS_MCUX_SYSCON
11 select CPU_CORTEX_M_HAS_SYSTICK
12 select SOC_RESET_HOOK
15 select CPU_CORTEX_M4
16 select CPU_CORTEX_M_HAS_DWT
17 select CPU_HAS_ARM_MPU
[all …]
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| /Zephyr-latest/soc/nordic/nrf54l/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
7 select SOC_COMPATIBLE_NRF54LX
8 select HAS_NRFX
9 select HAS_NORDIC_DRIVERS
10 select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
14 select ARM
15 select ARMV8_M_DSP
16 select CPU_CORTEX_M33
17 select CPU_HAS_ARM_MPU
18 select CPU_HAS_ICACHE
[all …]
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| /Zephyr-latest/dts/bindings/clock/ |
| D | nxp,kinetis-sim.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-sim"
14 pllfll-select:
17 description: pll/fll selection for clock system
19 er32k-select:
22 description: er32k selection for clock system
24 clkout-source:
26 description: clkout clock source
28 clkout-divider:
32 "#clock-cells":
[all …]
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| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.silabs | 2 # SPDX-License-Identifier: Apache-2.0
5 bool "Silabs Sleeptimer system clock driver"
8 select SOC_SILABS_SLEEPTIMER
9 select TICKLESS_CAPABLE
10 select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
13 and provides the standard "system clock driver" interfaces.
|
| D | Kconfig.stm32_lptim | 4 # SPDX-License-Identifier: Apache-2.0
6 DT_CHOSEN_STDBY_TIMER := st,lptim-stdby-timer
13 select TICKLESS_CAPABLE
14 select EXPERIMENTAL
17 and provides the standard "system clock driver" interfaces.
22 prompt "LPTIM clock value configuration"
24 This option is deprecated and configuration of LPTIM domain clock
30 Use LSI as LPTIM clock
35 Use LSE as LPTIM clock
54 depending on LPTIM input clock:
[all …]
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| D | Kconfig.riscv_machine | 1 # Copyright (c) 2014-2015 Wind River Systems, Inc.
3 # Copyright (c) 2019-2023 Intel Corp.
4 # SPDX-License-Identifier: Apache-2.0
16 select TICKLESS_CAPABLE
17 select TIMER_HAS_64BIT_CYCLE_COUNTER
20 timer driver. It provides the standard "system clock driver" interfaces.
28 Specifies the division ratio of the system clock supplied to the Machine Timer.
30 A clock obtained by dividing the system clock by a value of [2^N] is
33 Default case is N=0, this means use system clock as machine timer clock.
34 It is normal configuration for RISC-V machine clock.
|
| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/ |
| D | adsp_shim.h | 4 * SPDX-License-Identifier: Apache-2.0
15 * Power Management / Clock Control (HST) Registers
18 * and clock control operation for DSP FW.
32 * Power Management / Clock Control (ULP) Registers
35 * and clock control operation for DSP FW.
38 /* Power Management / Clock Capability */
41 /* HP RING Oscillator Clock Frequency */
44 /* XTAL Oscillator Clock Frequency */
47 /* LP RING Oscillator Clock Frequency */
50 /* Serial I/O RING Oscillator Clock Frequency */
[all …]
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| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/ |
| D | adsp_shim.h | 4 * SPDX-License-Identifier: Apache-2.0
15 * Power Management / Clock Control (HST) Registers
18 * and clock control operation for DSP FW.
32 * Power Management / Clock Control (ULP) Registers
35 * and clock control operation for DSP FW.
38 /* Power Management / Clock Capability */
41 /* HP RING Oscillator Clock Frequency */
44 /* XTAL Oscillator Clock Frequency */
47 /* LP RING Oscillator Clock Frequency */
50 /* Serial I/O RING Oscillator Clock Frequency */
[all …]
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| /Zephyr-latest/subsys/net/lib/ptp/ |
| D | Kconfig | 2 # SPDX-License-Identifier: Apache-2.0
6 select EXPERIMENTAL
7 select EVENTFD
8 select NET_SOCKETS
9 select NET_CONTEXT_PRIORITY
10 select NET_L2_PTP
21 module-dep = NET_LOG
22 module-str = Log level for PTP
23 module-help = Enable logs for the PTP stack.
53 prompt "PTP Clock Type"
[all …]
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| /Zephyr-latest/drivers/ethernet/ |
| D | Kconfig.stm32_hal | 5 # SPDX-License-Identifier: Apache-2.0
11 select USE_STM32_HAL_ETH
12 select NOCACHE_MEMORY if SOC_SERIES_STM32H7X && CPU_CORTEX_M7
13 select HWINFO
14 select ETH_DSA_SUPPORT
15 select PINCTRL
16 select MDIO if SOC_SERIES_STM32H5X || SOC_SERIES_STM32H7X
84 PHY's carrier status is re-evaluated.
119 bool "STM32 HAL PTP clock driver support"
123 Enable STM32 PTP clock support.
[all …]
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| /Zephyr-latest/drivers/disk/ |
| D | Kconfig.sdmmc | 3 # SPDX-License-Identifier: Apache-2.0
25 select SDMMC_STACK
35 select USE_STM32_HAL_SD if !SDMMC_STM32_EMMC
36 select USE_STM32_HAL_SD_EX if !SDMMC_STM32_EMMC && SOC_SERIES_STM32L4X
37 select USE_STM32_HAL_MMC if SDMMC_STM32_EMMC
38 select USE_STM32_HAL_MMC_EX if SDMMC_STM32_EMMC && SOC_SERIES_STM32L4X
39 select USE_STM32_LL_SDMMC
40 select USE_STM32_HAL_DMA if (SOC_SERIES_STM32L4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32F4X)
41 select DMA if $(DT_STM32_SDMMC_HAS_DMA) && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X)
42 select PINCTRL
[all …]
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