Lines Matching +full:clock +full:- +full:select
3 # Copyright (c) 2016-2023 Nordic Semiconductor ASA
4 # SPDX-License-Identifier: Apache-2.0
7 select ARM
8 select SOC_COMPATIBLE_NRF52X
9 select CPU_CORTEX_M4
10 select CPU_HAS_ARM_MPU
12 select HAS_NRFX
13 select HAS_NORDIC_DRIVERS
14 select HAS_NORDIC_RAM_CTRL
15 select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
16 select HAS_SWO
17 select HAS_POWEROFF
20 select CPU_CORTEX_M_HAS_DWT
21 select CPU_HAS_FPU
24 select SOC_COMPATIBLE_NRF52833
25 select CPU_CORTEX_M_HAS_DWT
26 select CPU_HAS_FPU
29 select CPU_CORTEX_M_HAS_DWT
30 select CPU_HAS_FPU
36 select DEPRECATED
42 regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
50 select DEPRECATED
63 select DEPRECATED
69 gpio-as-nreset;
73 bool "The instruction cache (I-Cache)"
85 clock so if clock is initiated in certain window, the clock may also fail
86 to start at reboot. A delay is added before starting LF clock to ensure
88 that clock is started later than 330 us after reset. If crystal oscillator
89 (XO) is used then low frequency clock initially starts with RC and then
112 64MHz clock at the same time as the peripheral that is using DMA is started.
127 Due to Anomaly 219 the low period of SCL clock is too short to meet