1# Nordic Semiconductor nRF52 MCU line
2
3# Copyright (c) 2016-2023 Nordic Semiconductor ASA
4# SPDX-License-Identifier: Apache-2.0
5
6config SOC_SERIES_NRF52X
7	select ARM
8	select SOC_COMPATIBLE_NRF52X
9	select CPU_CORTEX_M4
10	select CPU_HAS_ARM_MPU
11	imply XIP
12	select HAS_NRFX
13	select HAS_NORDIC_DRIVERS
14	select HAS_NORDIC_RAM_CTRL
15	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
16	select HAS_SWO
17	select HAS_POWEROFF
18
19config SOC_NRF52832
20	select CPU_CORTEX_M_HAS_DWT
21	select CPU_HAS_FPU
22
23config SOC_NRF52833
24	select SOC_COMPATIBLE_NRF52833
25	select CPU_CORTEX_M_HAS_DWT
26	select CPU_HAS_FPU
27
28config SOC_NRF52840
29	select CPU_CORTEX_M_HAS_DWT
30	select CPU_HAS_FPU
31
32if SOC_SERIES_NRF52X
33
34config SOC_DCDC_NRF52X
35	bool
36	select DEPRECATED
37	help
38	  This option is deprecated, use devicetree instead. Example
39	  configuration:
40
41	  &reg/reg1 {
42	    regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
43	  };
44
45	  Enable nRF52 series System on Chip DC/DC converter.
46
47config SOC_DCDC_NRF52X_HV
48	bool
49	depends on SOC_NRF52840_QIAA
50	select DEPRECATED
51	help
52	  This option is deprecated, use devicetree instead. Example
53	  configuration:
54
55	  &reg0 {
56	    status = "okay";
57	  };
58
59	  Enable nRF52 series System on Chip High Voltage DC/DC converter.
60
61config GPIO_AS_PINRESET
62	bool "[DEPRECATED] GPIO as pin reset (reset button)"
63	select DEPRECATED
64	help
65	  This option is deprecated, use devicetree instead. Example
66	  configuration:
67
68	  &uicr {
69	      gpio-as-nreset;
70	  };
71
72config NRF_ENABLE_ICACHE
73	bool "The instruction cache (I-Cache)"
74	depends on SOC_NRF52832 || SOC_NRF52833 || SOC_NRF52840
75	default y
76
77config NRF52_ANOMALY_132_DELAY_US
78	int "Anomaly 132 workaround delay (microseconds)"
79	default 330
80	range 0 330
81	depends on NRF52_ANOMALY_132_WORKAROUND
82	help
83	  Due to Anomaly 132 LF RC source may not start if restarted in certain
84	  window after stopping (230 us to 330 us). Software reset also stops the
85	  clock so if clock is initiated in certain window, the clock may also fail
86	  to start at reboot. A delay is added before starting LF clock to ensure
87	  that anomaly conditions are not met. Delay should be long enough to ensure
88	  that clock is started later than 330 us after reset. If crystal oscillator
89	  (XO) is used then low frequency clock initially starts with RC and then
90	  seamlessly switches to XO which has much longer startup time thus,
91	  depending on application, workaround may also need to be applied.
92	  Additional drivers initialization increases initialization time and delay
93	  may be shortened. Workaround is disabled by setting delay to 0.
94
95config NRF52_ANOMALY_198_WORKAROUND
96	bool "Anomaly 198 workaround"
97	default y
98	depends on SOC_NRF52840
99	depends on NRFX_SPIM3
100	help
101	  This anomaly applies to IC revisions "Engineering B" up to "3", the most
102	  recent one.
103
104config NRF52_ANOMALY_109_WORKAROUND
105	bool "Anomaly 109 workaround"
106	default y
107	depends on SOC_NRF52832
108	depends on NRFX_SPIS || NRFX_SPIM || NRFX_TWIM || NRFX_PWM
109	help
110	  Due to Anomaly 109 the first byte sent out by these peripherals is
111	  sometimes wrong. This occurs when the system enters IDLE and stops the
112	  64MHz clock at the same time as the peripheral that is using DMA is started.
113	  This anomaly applies to IC revisions up to "3", the most recent one.
114
115config NRF52_ANOMALY_109_WORKAROUND_EGU_INSTANCE
116	int "Anomaly 109 workaround EGU instance"
117	depends on NRF52_ANOMALY_109_WORKAROUND
118	range 0 5
119	default 5
120	help
121	  EGU instance used by the nRF52 Anomaly 109 workaround for PWM.
122
123endif # SOC_SERIES_NRF52X
124