# Nordic Semiconductor nRF52 MCU line

# Copyright (c) 2016-2023 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0

config SOC_SERIES_NRF52X
	select ARM
	select SOC_COMPATIBLE_NRF52X
	select CPU_CORTEX_M4
	select CPU_HAS_ARM_MPU
	imply XIP
	select HAS_NRFX
	select HAS_NORDIC_DRIVERS
	select HAS_NORDIC_RAM_CTRL
	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
	select HAS_SWO
	select HAS_POWEROFF

config SOC_NRF52832
	select CPU_CORTEX_M_HAS_DWT
	select CPU_HAS_FPU

config SOC_NRF52833
	select SOC_COMPATIBLE_NRF52833
	select CPU_CORTEX_M_HAS_DWT
	select CPU_HAS_FPU

config SOC_NRF52840
	select CPU_CORTEX_M_HAS_DWT
	select CPU_HAS_FPU

if SOC_SERIES_NRF52X

config SOC_DCDC_NRF52X
	bool
	select DEPRECATED
	help
	  This option is deprecated, use devicetree instead. Example
	  configuration:

	  &reg/reg1 {
	    regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
	  };

	  Enable nRF52 series System on Chip DC/DC converter.

config SOC_DCDC_NRF52X_HV
	bool
	depends on SOC_NRF52840_QIAA
	select DEPRECATED
	help
	  This option is deprecated, use devicetree instead. Example
	  configuration:

	  &reg0 {
	    status = "okay";
	  };

	  Enable nRF52 series System on Chip High Voltage DC/DC converter.

config GPIO_AS_PINRESET
	bool "[DEPRECATED] GPIO as pin reset (reset button)"
	select DEPRECATED
	help
	  This option is deprecated, use devicetree instead. Example
	  configuration:

	  &uicr {
	      gpio-as-nreset;
	  };

config NRF_ENABLE_ICACHE
	bool "The instruction cache (I-Cache)"
	depends on SOC_NRF52832 || SOC_NRF52833 || SOC_NRF52840
	default y

config NRF52_ANOMALY_132_DELAY_US
	int "Anomaly 132 workaround delay (microseconds)"
	default 330
	range 0 330
	depends on NRF52_ANOMALY_132_WORKAROUND
	help
	  Due to Anomaly 132 LF RC source may not start if restarted in certain
	  window after stopping (230 us to 330 us). Software reset also stops the
	  clock so if clock is initiated in certain window, the clock may also fail
	  to start at reboot. A delay is added before starting LF clock to ensure
	  that anomaly conditions are not met. Delay should be long enough to ensure
	  that clock is started later than 330 us after reset. If crystal oscillator
	  (XO) is used then low frequency clock initially starts with RC and then
	  seamlessly switches to XO which has much longer startup time thus,
	  depending on application, workaround may also need to be applied.
	  Additional drivers initialization increases initialization time and delay
	  may be shortened. Workaround is disabled by setting delay to 0.

config NRF52_ANOMALY_198_WORKAROUND
	bool "Anomaly 198 workaround"
	default y
	depends on SOC_NRF52840
	depends on NRFX_SPIM3
	help
	  This anomaly applies to IC revisions "Engineering B" up to "3", the most
	  recent one.

config NRF52_ANOMALY_109_WORKAROUND
	bool "Anomaly 109 workaround"
	default y
	depends on SOC_NRF52832
	depends on NRFX_SPIS || NRFX_SPIM || NRFX_TWIM || NRFX_PWM
	help
	  Due to Anomaly 109 the first byte sent out by these peripherals is
	  sometimes wrong. This occurs when the system enters IDLE and stops the
	  64MHz clock at the same time as the peripheral that is using DMA is started.
	  This anomaly applies to IC revisions up to "3", the most recent one.

config NRF52_ANOMALY_109_WORKAROUND_EGU_INSTANCE
	int "Anomaly 109 workaround EGU instance"
	depends on NRF52_ANOMALY_109_WORKAROUND
	range 0 5
	default 5
	help
	  EGU instance used by the nRF52 Anomaly 109 workaround for PWM.

endif # SOC_SERIES_NRF52X