1 /* 2 * Copyright (c) 2021 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ 7 #define ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ 8 9 #ifndef _ASMLANGUAGE 10 11 #include <zephyr/sys/util.h> 12 13 /** 14 * DfPMCCH 15 * Power Management / Clock Control (HST) Registers 16 * 17 * These registers block (HST domain) are for general power management 18 * and clock control operation for DSP FW. 19 */ 20 struct ace_dfpmcch { 21 uint32_t dfspsreq; /* Offset: 0x00 */ 22 uint32_t _unused0[3]; 23 uint32_t dfspsrsp; /* Offset: 0x10 */ 24 uint32_t _unused1[1]; 25 uint32_t svcfg; /* Offset: 0x18 */ 26 uint32_t dfltrc; /* Offset: 0x1c */ 27 uint32_t _unused2[8]; 28 }; 29 30 /** 31 * DfPMCCU 32 * Power Management / Clock Control (ULP) Registers 33 * 34 * These registers block (ULP domain) are for general power management 35 * and clock control operation for DSP FW. 36 */ 37 struct ace_dfpmccu { 38 /* Power Management / Clock Capability */ 39 uint32_t dfpmccap; /* Offset: 0x00 */ 40 41 /* HP RING Oscillator Clock Frequency */ 42 uint32_t dfhrosccf; /* Offset: 0x04 */ 43 44 /* XTAL Oscillator Clock Frequency */ 45 uint32_t dfxosccf; /* Offset: 0x08 */ 46 47 /* LP RING Oscillator Clock Frequency */ 48 uint32_t dflrosccf; /* Offset: 0x0c */ 49 50 /* Serial I/O RING Oscillator Clock Frequency */ 51 uint32_t dfsiorosccf; /* Offset: 0x10 */ 52 53 /* High Speed I/O RING Oscillator Clock Frequency */ 54 uint32_t dfhsiorosccf; /* Offset: 0x14 */ 55 56 /* Integrated PLL / ROSC Clock Frequency */ 57 uint32_t dfipllrosccf; /* Offset: 0x18 */ 58 59 /* Integrated RING Oscillator Clock Voltage */ 60 uint32_t dfirosccv; /* Offset: 0x1c */ 61 62 /* Fabric Clock Frequency Divider */ 63 uint32_t dffbrcfd; /* Offset: 0x20 */ 64 65 /* ACE PLL IP Pointer */ 66 uint32_t dfapllptr; /* Offset: 0x24 */ 67 uint32_t _unused0[20]; 68 69 /* Clock Control */ 70 uint32_t dfclkctl; /* Offset: 0x78 */ 71 72 /* Clock Status */ 73 uint32_t dfclksts; /* Offset: 0x7c */ 74 75 /* Integrated Clock Control Register */ 76 uint32_t dfintclkctl; /* Offset: 0x80 */ 77 78 /* Integrated Clock Status Register */ 79 uint32_t dfcrosts; /* Offset: 0x84 */ 80 81 /* Integrated Clock Divider Register */ 82 uint32_t dfcrodiv; /* Offset: 0x88 */ 83 uint32_t _unused1[1]; 84 85 /* Power Control */ 86 uint16_t dfpwrctl; /* Offset: 0x90 */ 87 88 /* Power Status */ 89 uint16_t dfpwrsts; /* Offset: 0x92 */ 90 uint32_t _unused2[1]; 91 92 /* Low Power Sequencer DMA Select 0 */ 93 uint32_t dflpsdmas0; /* Offset: 0x98 */ 94 95 /* Low Power Sequencer DMA Select 1 */ 96 uint32_t dflpsdmas1; /* Offset: 0x9c */ 97 98 uint32_t _unused3[1]; 99 100 /* LDO Control */ 101 uint32_t dfldoctl; /* Offset: 0xa4 */ 102 uint32_t _unused4[2]; 103 104 /* Low Power Sequencer Audio Link Hub Stream Select 0 */ 105 uint32_t dflpsalhsso; /* Offset: 0xb0 */ 106 107 /* Low Power Sequencer Audio Link Hub Stream Select 1 */ 108 uint32_t dflpsalhss1; /* Offset: 0xb4 */ 109 110 /* Low Power Sequencer Audio Link Hub Stream Select 2 */ 111 uint32_t dflpsalhss2; /* Offset: 0xb8 */ 112 113 /* Low Power Sequencer Audio Link Hub Stream Select 3 */ 114 uint32_t dflpsalhss3; /* Offset: 0xbc */ 115 uint32_t _unused5[10]; 116 }; 117 118 #define ACE_DfPMCCH (*((volatile struct ace_dfpmcch *)DT_REG_ADDR(DT_NODELABEL(dfpmcch)))) 119 #define ACE_DfPMCCU (*((volatile struct ace_dfpmccu *)DT_REG_ADDR(DT_NODELABEL(dfpmccu)))) 120 121 122 #define ADSP_TTSCAP_OFFSET 0x00 123 #define ADSP_RTCWC_OFFSET 0x08 124 #define ADSP_DSPWCCTL_OFFSET 0x10 125 #define ADSP_DSPWCSTS_OFFSET 0x12 126 #define ADSP_DSPWCAV_OFFSET 0x18 127 #define ADSP_DSPWC_OFFSET 0x20 128 #define ADSP_DSPWCTCS_OFFSET 0x28 129 #define ADSP_DSPWCT0C_OFFSET 0x30 130 #define ADSP_DSPWCT1C_OFFSET 0x38 131 #define ADSP_TSCTRL_OFFSET 0x40 132 #define ADSP_ISCS_OFFSET 0x44 133 #define ADSP_LSCS_OFFSET 0x48 134 #define ADSP_DWCCS_OFFSET 0x50 135 #define ADSP_ARTCS_OFFSET 0x58 136 #define ADSP_LWCCS_OFFSET 0x60 137 #define ADSP_CLTSYNC_OFFSET 0x70 138 139 140 141 #define ADSP_SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c)) 142 143 #define ADSP_SHIM_TSCTRL_NTK BIT(31) 144 #define ADSP_SHIM_TSCTRL_IONTE BIT(30) 145 #define ADSP_SHIM_TSCTRL_DMATS GENMASK(13, 12) 146 #define ADSP_SHIM_TSCTRL_CLNKS GENMASK(11, 10) 147 #define ADSP_SHIM_TSCTRL_HHTSE BIT(7) 148 #define ADSP_SHIM_TSCTRL_LWCS BIT(6) 149 #define ADSP_SHIM_TSCTRL_ODTS BIT(5) 150 #define ADSP_SHIM_TSCTRL_CDMAS GENMASK(4, 0) 151 152 #endif /* _ASMLANGUAGE */ 153 154 #define ACE_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */ 155 156 #define ADSP_DMWBA_ENABLE BIT(0) 157 #define ADSP_DMWBA_READONLY BIT(1) 158 159 #define ADSP_CLKCTL_OSC_SOURCE_MASK (3<<2) 160 #define ADSP_CLKCTL_OSC_REQUEST_MASK (~BIT_MASK(28)) 161 162 /** LDO Control */ 163 #define ADSP_DSPRA_ADDRESS (0x71A60) 164 #define ADSP_LPGPDMACxO_ADDRESS(x) (ADSP_DSPRA_ADDRESS + 0x0000 + 0x0002*(x)) 165 #define ADSP_DSPIOPO_ADDRESS (ADSP_DSPRA_ADDRESS + 0x0008) 166 #define ADSP_GENO_ADDRESS (ADSP_DSPRA_ADDRESS + 0x000C) 167 #define ADSP_DSPALHO_ADDRESS (ADSP_DSPRA_ADDRESS + 0x0010) 168 169 170 #define DSP_INIT_IOPO ADSP_DSPIOPO_ADDRESS 171 #define IOPO_DMIC_FLAG BIT(0) 172 #define IOPO_DSPKOSEL_FLAG BIT(1) 173 #define IOPO_ANCOSEL_FLAG BIT(2) 174 #define IOPO_DMIXOSEL_FLAG BIT(3) 175 #define IOPO_SLIMOSEL_FLAG BIT(4) 176 #define IOPO_SNDWOSEL_FLAG BIT(5) 177 #define IOPO_SLIMDOSEL_FLAG BIT(20) 178 #define IOPO_I2SSEL_MASK (0x7 << 0x8) 179 180 #define DSP_INIT_GENO ADSP_GENO_ADDRESS 181 #define GENO_MDIVOSEL BIT(1) 182 #define GENO_DIOPTOSEL BIT(2) 183 184 #define ADSP_FORCE_DECOUPLED_HDMA_L1_EXIT_BIT BIT(1) 185 186 #endif /* ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ */ 187
