Lines Matching +full:clock +full:- +full:select

2 # SPDX-License-Identifier: Apache-2.0
5 	select CPU_HAS_FPU if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" || RISCV_ISA_EXT_M
6 	select HAS_PM
7 	select ARCH_HAS_CUSTOM_CPU_IDLE
8 	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
9 	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
14 	select RISCV
15 	select ATOMIC_OPERATIONS_BUILTIN
16 	select RISCV_ISA_RV32I
17 	select RISCV_ISA_EXT_ZICSR
18 	select RISCV_ISA_EXT_ZIFENCEI
20 	# https://www.ite.com.tw/uploads/product_download/it81202-bx-chip-errata.pdf
21 	select RISCV_ISA_EXT_M if !(SOC_IT81302BX || SOC_IT81202BX)
22 	select RISCV_ISA_EXT_A
23 	select RISCV_ISA_EXT_C
51 	select SOC_IT8XXX2_REG_SET_V1
52 	select SOC_IT8XXX2_USBPD_PHY_V1
55 	select SOC_IT8XXX2_REG_SET_V1
56 	select SOC_IT8XXX2_USBPD_PHY_V1
59 	select SOC_IT8XXX2_REG_SET_V1
60 	select SOC_IT8XXX2_USBPD_PHY_V2
63 	select SOC_IT8XXX2_REG_SET_V1
64 	select SOC_IT8XXX2_USBPD_PHY_V2
67 	select SOC_IT8XXX2_REG_SET_V1
68 	select SOC_IT8XXX2_USBPD_PHY_V2
71 	select SOC_IT8XXX2_REG_SET_V1
72 	select SOC_IT8XXX2_USBPD_PHY_V2
75 	select SOC_IT8XXX2_REG_SET_V2
76 	select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
77 	select SOC_IT8XXX2_USBPD_PHY_V2
80 	select SOC_IT8XXX2_REG_SET_V2
81 	select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
82 	select SOC_IT8XXX2_USBPD_PHY_V2
85 	select SOC_IT8XXX2_REG_SET_V2
86 	select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
87 	select SOC_IT8XXX2_USBPD_PHY_V2
90 	select SOC_IT8XXX2_REG_SET_V2
91 	select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
92 	select SOC_IT8XXX2_USBPD_PHY_V2
95 	select SOC_IT8XXX2_REG_SET_V2
96 	select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
97 	select SOC_IT8XXX2_USBPD_PHY_V2
100 	select SOC_IT8XXX2_REG_SET_V2
101 	select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
102 	select SOC_IT8XXX2_USBPD_PHY_V2
107 	select FLASH
118 	  On IT81202 (128-pins package), the pins of GPIO group K and L aren't
119 	  bonding with pad. So we configure these pins as internal pull-down
127 	  floating internally. We need to enable internal pull-down for the pin
145 	  The clock_frequency of ite,it8xxx2-i2c node (i2c0, i2c1, and i2c2) will
152 	  - GPIOA0 -> TCK
153 	  - GPIOA1 -> TDI
154 	  - GPIOA4 -> TDO
155 	  - GPIOA5 -> TMS
156 	  - GPIOA6 -> TRST
163 	  The LCVCO is a highly precise clock controller used for
166 	  the accuracy of the USB clock.
169 	prompt "Clock source for PLL reference clock"
172 	bool "Use the +/-2.3% internal clock generator"
175 	bool "Use external 32.768 kHz clock source"
192 	select SOC_IT8XXX2_USE_ILM
196 	  Flash. This can significantly improve performance when under I-cache
207 	select SOC_IT8XXX2_USE_ILM
208 	select SOC_IT8XXX2_LIBRARY_TO_RAM
215 	select SOC_IT8XXX2_USE_ILM
216 	select SOC_IT8XXX2_LIBRARY_TO_RAM
222 	select SOC_IT8XXX2_USE_ILM
223 	select SOC_IT8XXX2_LIBRARY_TO_RAM