Lines Matching +full:clock +full:- +full:select
3 # SPDX-License-Identifier: Apache-2.0
6 select CPU_CORTEX_M33
7 select CLOCK_CONTROL
8 select CPU_CORTEX_M_HAS_DWT
9 select ARM
10 select HAS_PM
11 select HAS_POWEROFF
12 select CPU_HAS_ARM_SAU
13 select CPU_HAS_ARM_MPU
14 select CPU_HAS_FPU
15 select SOC_RESET_HOOK
16 select ARMV8_M_DSP
17 select ARM_TRUSTZONE_M
18 select CPU_CORTEX_M_HAS_SYSTICK
19 select HAS_MCUX
20 select HAS_MCUX_SYSCON
21 select HAS_MCUX_FLEXCOMM
22 select HAS_MCUX_FLEXSPI
23 select HAS_MCUX_CACHE
24 select HAS_MCUX_LPC_DMA
25 select HAS_MCUX_LPADC
26 select HAS_MCUX_OS_TIMER
27 select HAS_MCUX_LPC_RTC
28 select HAS_MCUX_TRNG
29 select HAS_MCUX_SCTIMER
30 select HAS_MCUX_USDHC1
31 select HAS_MCUX_USDHC2
32 select HAS_MCUX_USB_LPCIP3511
33 select HAS_MCUX_CTIMER
34 select SOC_EARLY_INIT_HOOK
37 select XTENSA
38 …select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "…
39 select XTENSA_RESET_VECTOR
40 select XTENSA_USE_CORE_CRT1
59 prompt "Clock source for Flexcomm0"
63 bool "FRG is source of Flexcomm0 clock"
66 bool "FRO_DIV4 is source of Flexcomm0 clock"
71 prompt "Clock source for MIPI DPHY"
75 bool "AUX1_PLL is source of MIPI_DPHY clock"
78 bool "FRO 192/96M is source of MIPI_DPHY clock"