1# Nordic Semiconductor nRF54 MCU line
2
3# Copyright (c) 2024 Nordic Semiconductor ASA
4# SPDX-License-Identifier: Apache-2.0
5
6config SOC_SERIES_NRF54LX
7	select SOC_COMPATIBLE_NRF54LX
8	select HAS_NRFX
9	select HAS_NORDIC_DRIVERS
10	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
11
12config SOC_NRF54L_CPUAPP_COMMON
13	bool
14	select ARM
15	select ARMV8_M_DSP
16	select CPU_CORTEX_M33
17	select CPU_HAS_ARM_MPU
18	select CPU_HAS_ICACHE
19	select CPU_HAS_ARM_SAU
20	select CPU_HAS_FPU
21	select HAS_HW_NRF_RADIO_IEEE802154
22	select HAS_POWEROFF
23	select HAS_NORDIC_RAM_CTRL
24
25config SOC_NRF54L05_CPUAPP
26	select SOC_NRF54L_CPUAPP_COMMON
27
28config SOC_NRF54L10_CPUAPP
29	select SOC_NRF54L_CPUAPP_COMMON
30
31config SOC_NRF54L15_CPUAPP
32	select SOC_NRF54L_CPUAPP_COMMON
33
34config SOC_NRF54L05_CPUFLPR
35	select RISCV_CORE_NORDIC_VPR
36
37config SOC_NRF54L10_CPUFLPR
38	select RISCV_CORE_NORDIC_VPR
39
40config SOC_NRF54L15_CPUFLPR
41	select RISCV_CORE_NORDIC_VPR
42
43config SOC_NRF54L20_ENGA_CPUAPP
44	select SOC_NRF54L_CPUAPP_COMMON
45
46if SOC_SERIES_NRF54LX
47
48config SOC_NRF54LX_SKIP_CLOCK_CONFIG
49	bool "Skip clock frequency configuration in system initialization"
50	help
51	  With this option, the CPU clock frequency is not set during system initialization.
52	  The CPU runs with the default, hardware-selected frequency.
53
54config SOC_NRF54LX_DISABLE_FICR_TRIMCNF
55	bool "Disable trimming of the device"
56	default y if TRUSTED_EXECUTION_NONSECURE
57	help
58	  Disable trimming of the device. When the device is trimmed it
59	  will copy all the trimming values from FICR into the target
60	  addresses.
61
62config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE
63	bool "Skip disabling glitch detector"
64	default y if TRUSTED_EXECUTION_NONSECURE
65	help
66	  With this option, the glitch detector is not disabled during system initialization.
67	  The CPU runs with the default state of glitch detector.
68
69config SOC_NRF_FORCE_CONSTLAT
70	bool "Force constant-latency mode"
71	help
72	  In constant latency mode the CPU wakeup latency and the PPI task response
73	  will be constant and kept at a minimum. This is secured by forcing a set
74	  of base resources on while in sleep. The advantage of having a constant
75	  and predictable latency will be at the cost of having increased power consumption.
76
77endif # SOC_SERIES_NRF54LX
78