1# LPC LPC54XXX MCU line 2 3# Copyright 2017, 2024 NXP 4# SPDX-License-Identifier: Apache-2.0 5 6config SOC_SERIES_LPC54XXX 7 select ARM 8 select HAS_MCUX 9 select HAS_MCUX_FLEXCOMM 10 select HAS_MCUX_SYSCON 11 select CPU_CORTEX_M_HAS_SYSTICK 12 select SOC_RESET_HOOK 13 14config SOC_LPC54114_M4 15 select CPU_CORTEX_M4 16 select CPU_CORTEX_M_HAS_DWT 17 select CPU_HAS_ARM_MPU 18 select CPU_HAS_FPU 19 select SOC_RESET_HOOK 20 select CLOCK_CONTROL 21 select HAS_MCUX_IAP_LEGACY 22 23config SOC_LPC54114_M0 24 select CPU_CORTEX_M0PLUS 25 select CPU_CORTEX_M_HAS_VTOR 26 select CLOCK_CONTROL 27 28config MCUX_CORE_SUFFIX 29 default "_cm4" if SOC_LPC54114_M4 30 default "_cm0plus" if SOC_LPC54114_M0 31 32if SOC_SERIES_LPC54XXX 33 34config SECOND_CORE_MCUX 35 bool "LPC54114 Cortex-M0 second core" 36 help 37 Driver for second core startup 38 39config SECOND_CORE_BOOT_ADDRESS_MCUX 40 depends on SECOND_CORE_MCUX 41 hex "Address the second core will boot at" 42 default 0x20010000 43 help 44 This is the address the second core will boot from. Additionally this 45 address is where we will copy the SECOND_IMAGE to. We default this to 46 the base of SRAM1. 47 48# Workaround for not being able to have commas in macro arguments 49DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition 50 51# Move the LMA address of second core into flash 52config BUILD_OUTPUT_ADJUST_LMA 53 depends on SECOND_CORE_MCUX && SOC_LPC54114_M0 54 default "-0x20010000+\ 55 $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))" 56 57config BUILD_OUTPUT_INFO_HEADER 58 default y 59 depends on SECOND_CORE_MCUX && SOC_LPC54114_M0 60 61config LPC54XXX_SRAM2_CLOCK 62 bool "Clock LPC54XXX SRAM2" 63 default y 64 help 65 SRAM2 ram bank is disabled out of reset. By default, CMSIS SystemInit 66 will enable the clock to this RAM bank. Disable this Kconfig to leave 67 this ram bank untouched out of reset. 68 69endif # SOC_SERIES_LPC54XXX 70
