| /Zephyr-latest/drivers/dai/nxp/esai/ |
| D | esai.h | 210 /* enable/disable the HCLK prescaler */
212 /* controls the divison value of HCLK (i.e: TPM0-TPM7) */
214 /* controls the division value of HCLK before reaching
218 /* should the HCLK divison be bypassed or not?
219 * If in bypass, HCLK pad will be the same as EXTAL
223 /* HCLK direction - input or output */
225 /* HCLK source - EXTAL or IPG clock */
227 /* HCLK polarity - LOW or HIGH */
486 LOG_DBG("HCLK prescaler enable: %d", cfg->hclk_prescaler_en); in esai_dump_xceiver_config()
487 LOG_DBG("HCLK divider ratio: %d", cfg->hclk_div_ratio); in esai_dump_xceiver_config()
[all …]
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| D | esai.c | 26 * signal is referred to as HCLK.
27 * d) HCLK obtained from c) can be further divided by 1
51 LOG_ERR("HCLK rate cannot be higher than EXTAL rate"); in esai_get_clock_rate_config()
68 LOG_ERR("HCLK prescaler bypass with divider bypass is not supported"); in esai_get_clock_rate_config()
75 /* check if HCLK is in (EXTAL_RATE / 2, EXTAL_RATE). If so, in esai_get_clock_rate_config()
79 LOG_ERR("HCLK rate cannot be higher than EXTAL's rate divided by 2"); in esai_get_clock_rate_config()
83 /* compute HCLK configuration - only required if HCLK pad output is used */ in esai_get_clock_rate_config()
86 /* HCLK rate from pad is the same as EXTAL rate */ in esai_get_clock_rate_config()
96 /* can't obtain HCLK w/o prescaler */ in esai_get_clock_rate_config()
105 LOG_ERR("cannot obtain HCLK rate %u from EXTAL rate %u", in esai_get_clock_rate_config()
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| /Zephyr-latest/soc/atmel/sam/common/ |
| D | Kconfig | 72 This divisor defines a ratio between processor clock (HCLK)
74 MCK = HCLK / MDIV
84 For JTAG debugging CPU clock (HCLK) should not stop. In order to
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| /Zephyr-latest/dts/bindings/memory-controllers/ |
| D | st,stm32-fmc-nor-psram.yaml | 134 Number of HCLK cycles to configure the duration of
139 Number of HCLK cycles to configure the duration of
144 Number of HCLK cycles to configure the duration of
150 Number of HCLK cycles to configure the duration of
156 HCLK cycles. This parameter can be a value
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| /Zephyr-latest/soc/microchip/mec/mec15xx/ |
| D | Kconfig | 27 This divisor defines a ratio between processor clock (HCLK)
29 HCLK = MCK / PROC_CLK_DIV
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| /Zephyr-latest/drivers/entropy/ |
| D | entropy_sam.c | 46 * MCK may not be smaller than HCLK/4, so it should not take in entropy_sam_wait_ready()
47 * more than 336 HCLK ticks. Assuming the CPU can do 1 in entropy_sam_wait_ready()
48 * instruction per HCLK the number of times to loop before in entropy_sam_wait_ready()
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| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32h7-rcc.yaml | 15 Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
54 D1 Domain, CPU1 clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
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| D | st,stm32h7rs-rcc.yaml | 15 Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
62 CPU clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
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| D | st,stm32wba-rcc.yaml | 83 (HCLK) based on system frequency input. AKA HPRE.
84 The HCLK clocks CPU, AHB1, AHB2, memories and DMA.
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| /Zephyr-latest/soc/st/stm32/stm32mp1x/ |
| D | soc.c | 30 /* Update CMSIS SystemCoreClock variable (HCLK) */ in soc_early_init_hook()
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| /Zephyr-latest/soc/nuvoton/numicro/m48x/ |
| D | soc.c | 27 /* Set both PCLK0 and PCLK1 as HCLK/2 */ in soc_reset_hook()
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| /Zephyr-latest/soc/st/stm32/stm32f1x/ |
| D | soc.c | 31 /* Update CMSIS SystemCoreClock variable (HCLK) */ in soc_early_init_hook()
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| /Zephyr-latest/soc/atmel/sam/sam3x/ |
| D | soc.c | 79 * Processor Clock (HCLK) = 84 MHz. in clock_init()
105 * keep Processor Clock (HCLK) and thus be able to debug in soc_reset_hook()
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| /Zephyr-latest/soc/st/stm32/stm32f3x/ |
| D | soc.c | 28 /* Update CMSIS SystemCoreClock variable (HCLK) */ in soc_early_init_hook()
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| /Zephyr-latest/soc/st/stm32/stm32u0x/ |
| D | soc.c | 33 /* Update CMSIS SystemCoreClock variable (HCLK) */ in soc_early_init_hook()
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| /Zephyr-latest/soc/st/stm32/stm32c0x/ |
| D | soc.c | 32 /* Update CMSIS SystemCoreClock variable (HCLK) */ in soc_early_init_hook()
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| /Zephyr-latest/soc/st/stm32/stm32f4x/ |
| D | soc.c | 33 /* Update CMSIS SystemCoreClock variable (HCLK) */ in soc_early_init_hook()
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| /Zephyr-latest/soc/st/stm32/stm32f7x/ |
| D | soc.c | 35 /* Update CMSIS SystemCoreClock variable (HCLK) */ in soc_early_init_hook()
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| /Zephyr-latest/soc/st/stm32/stm32wlx/ |
| D | soc.c | 37 /* Update CMSIS SystemCoreClock variable (HCLK) */ in soc_early_init_hook()
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/ |
| D | pll_csi_ahb_2_100.overlay | 29 ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
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| D | pll_hse24_ahb_2_100.overlay | 30 ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/ |
| D | pll_msis_ahb_2_40.overlay | 33 ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
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| /Zephyr-latest/dts/arm/silabs/ |
| D | efr32bg2x.dtsi | 26 hclk: hclk { label
36 clocks = <&hclk>;
50 clocks = <&hclk>;
99 clocks = <&hclk>;
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| D | efr32mg21.dtsi | 26 hclk: hclk { label
36 clocks = <&hclk>;
50 clocks = <&hclk>;
57 clocks = <&hclk>;
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| /Zephyr-latest/soc/st/stm32/stm32f2x/ |
| D | soc.c | 34 /* Update CMSIS SystemCoreClock variable (HCLK) */ in soc_early_init_hook()
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