1 /*
2  * Copyright (c) 2016 Open-RnD Sp. z o.o.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file
9  * @brief System/hardware module for STM32F1 processor
10  */
11 
12 #include <zephyr/device.h>
13 #include <zephyr/init.h>
14 
15 #include <stm32_ll_system.h>
16 
17 #include <cmsis_core.h>
18 
19 /**
20  * @brief Perform basic hardware initialization at boot.
21  *
22  * This needs to be run from the very beginning.
23  */
soc_early_init_hook(void)24 void soc_early_init_hook(void)
25 {
26 #ifdef FLASH_ACR_PRFTBE
27 	/* Enable ART Accelerator prefetch */
28 	LL_FLASH_EnablePrefetch();
29 #endif
30 
31 	/* Update CMSIS SystemCoreClock variable (HCLK) */
32 	/* At reset, system core clock is set to 8 MHz from HSI */
33 	SystemCoreClock = 8000000;
34 }
35