Lines Matching full:hclk
210 /* enable/disable the HCLK prescaler */
212 /* controls the divison value of HCLK (i.e: TPM0-TPM7) */
214 /* controls the division value of HCLK before reaching
218 /* should the HCLK divison be bypassed or not?
219 * If in bypass, HCLK pad will be the same as EXTAL
223 /* HCLK direction - input or output */
225 /* HCLK source - EXTAL or IPG clock */
227 /* HCLK polarity - LOW or HIGH */
486 LOG_DBG("HCLK prescaler enable: %d", cfg->hclk_prescaler_en); in esai_dump_xceiver_config()
487 LOG_DBG("HCLK divider ratio: %d", cfg->hclk_div_ratio); in esai_dump_xceiver_config()
489 LOG_DBG("HCLK bypass: %d", cfg->hclk_bypass); in esai_dump_xceiver_config()
491 LOG_DBG("HCLK direction: %d", cfg->hclk_dir); in esai_dump_xceiver_config()
492 LOG_DBG("HCLK source: %d", cfg->hclk_src); in esai_dump_xceiver_config()
493 LOG_DBG("HCLK polarity: %d", cfg->hclk_polarity); in esai_dump_xceiver_config()