1# Copyright (c) 2024, STMicroelectronics
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32 Reset and Clock controller node for STM32H7RS devices
6  This node is in charge of system clock ('SYSCLK') source selection and
7  System Clock Generation.
8
9  Configuring STM32 Reset and Clock controller node:
10
11  System clock source should be selected amongst the clock nodes available in "clocks"
12  node (typically 'clk_hse, clk_csi', 'pll', ...).
13  As part of this node configuration, SYSCLK frequency should also be defined, using
14  "clock-frequency" property.
15  Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
16  prescaler properties.
17  Here is an example of correctly configured rcc node:
18  &rcc {
19           clocks = <&pll>;  /* Set pll as SYSCLK source */
20           clock-frequency = <DT_FREQ_M(280)>; /* SYSCLK runs at 280MHz */
21           dcpre = <1>;
22           hpre = <1>;
23           ppre1 = <1>;
24           ppre2 = <1>;
25           ppre4 = <1>;
26           ppre5 = <1>;
27  }
28
29  Confere st,stm32-rcc binding for information about domain clocks configuration.
30
31compatible: "st,stm32h7rs-rcc"
32
33include: [clock-controller.yaml, base.yaml]
34
35properties:
36  reg:
37    required: true
38
39  "#clock-cells":
40    const: 2
41
42  clock-frequency:
43    required: true
44    type: int
45    description: |
46      default frequency in Hz for clock output
47
48  dcpre:
49    type: int
50    required: true
51    enum:
52      - 1
53      - 2
54      - 4
55      - 8
56      - 16
57      - 64
58      - 128
59      - 256
60      - 512
61    description: |
62        CPU clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
63        lower than SYSCLK frequency (actual core frequency).
64        Zephyr doesn't make a difference today between these two clocks.
65        Changing this prescaler is not allowed until it is made possible to
66        use them independently in Zephyr clock subsystem.
67
68  hpre:
69    type: int
70    required: true
71    description: |
72        peripheral clock to the Bus Matrix APB (1/2/4/5) and AHB(1/2/3/4/5) peripheral
73        divider of the CPU clock by this  prescaler (BMPRE register)
74    enum:
75      - 1
76      - 2
77      - 4
78      - 8
79      - 16
80      - 64
81      - 128
82      - 256
83      - 512
84
85  ppre1:
86    type: int
87    required: true
88    description: |
89        APB1 peripheral prescaler
90    enum:
91      - 1
92      - 2
93      - 4
94      - 8
95      - 16
96
97  ppre2:
98    type: int
99    required: true
100    description: |
101        APB2 peripheral prescaler
102    enum:
103      - 1
104      - 2
105      - 4
106      - 8
107      - 16
108
109  ppre4:
110    type: int
111    required: true
112    description: |
113        APB4 peripheral prescaler
114    enum:
115      - 1
116      - 2
117      - 4
118      - 8
119      - 16
120
121  ppre5:
122    type: int
123    required: true
124    description: |
125        APB5 peripheral prescaler
126    enum:
127      - 1
128      - 2
129      - 4
130      - 8
131      - 16
132
133clock-cells:
134  - bus
135  - bits
136