1 /*
2  * Copyright (c) 2018 Yurii Hamann
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file
9  * @brief System/hardware module for STM32F7 processor
10  */
11 
12 #include <zephyr/kernel.h>
13 #include <zephyr/device.h>
14 #include <zephyr/init.h>
15 #include <zephyr/cache.h>
16 #include <soc.h>
17 
18 #include <cmsis_core.h>
19 #include <stm32_ll_system.h>
20 
21 /**
22  * @brief Perform basic hardware initialization at boot.
23  *
24  * This needs to be run from the very beginning.
25  */
soc_early_init_hook(void)26 void soc_early_init_hook(void)
27 {
28 	/* Enable ART Flash cache accelerator and prefetch */
29 	LL_FLASH_EnableART();
30 	LL_FLASH_EnablePrefetch();
31 
32 	sys_cache_instr_enable();
33 	sys_cache_data_enable();
34 
35 	/* Update CMSIS SystemCoreClock variable (HCLK) */
36 	/* At reset, system core clock is set to 16 MHz from HSI */
37 	SystemCoreClock = 16000000;
38 }
39