1 /*
2  * Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file
9  * @brief System/hardware module for STM32C0 processor
10  */
11 
12 #include <zephyr/device.h>
13 #include <zephyr/init.h>
14 #include <zephyr/linker/linker-defs.h>
15 #include <string.h>
16 
17 #include <stm32_ll_system.h>
18 
19 #include <cmsis_core.h>
20 
21 /**
22  * @brief Perform basic hardware initialization at boot.
23  *
24  * This needs to be run from the very beginning.
25  */
soc_early_init_hook(void)26 void soc_early_init_hook(void)
27 {
28 	/* Enable ART Accelerator I-cache and prefetch */
29 	LL_FLASH_EnableInstCache();
30 	LL_FLASH_EnablePrefetch();
31 
32 	/* Update CMSIS SystemCoreClock variable (HCLK) */
33 	/* At reset, system core clock is set to 48 MHz from HSI */
34 	SystemCoreClock = 48000000;
35 }
36