1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32 Reset and Clock controller node for STM32H7 devices
6  This node is in charge of system clock ('SYSCLK') source selection and
7  System Clock Generation.
8
9  Configuring STM32 Reset and Clock controller node:
10
11  System clock source should be selected amongst the clock nodes available in "clocks"
12  node (typically 'clk_hse, clk_csi', 'pll', ...).
13  As part of this node configuration, SYSCLK frequency should also be defined, using
14  "clock-frequency" property.
15  Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
16  prescaler properties.
17  Here is an example of correctly configured rcc node:
18  &rcc {
19           clocks = <&pll>;  /* Set pll as SYSCLK source */
20           clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
21           d1cpre = <1>;
22           hpre = <1>;
23           d1ppre = <1>;
24           d2ppre1 = <1>;
25           d2ppre2 = <1>;
26           d3ppre = <1>;
27  }
28
29  Confere st,stm32-rcc binding for information about domain clocks configuration.
30
31compatible: "st,stm32h7-rcc"
32
33include: [clock-controller.yaml, base.yaml]
34
35properties:
36  reg:
37    required: true
38
39  "#clock-cells":
40    const: 2
41
42  clock-frequency:
43    required: true
44    type: int
45    description: |
46      default frequency in Hz for clock output
47
48  d1cpre:
49    type: int
50    required: true
51    enum:
52      - 1
53    description: |
54        D1 Domain, CPU1 clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
55        lower than SYSCLK frequency (actual core frequency).
56        Zephyr doesn't make a difference today between these two clocks.
57        Changing this prescaler is not allowed until it is made possible to
58        use them independently in Zephyr clock subsystem.
59
60  hpre:
61    type: int
62    required: true
63    description: |
64        D2 domain, CPU2 core clock and AHB(1/2/3/4) peripheral prescaler
65    enum:
66      - 1
67      - 2
68      - 4
69      - 8
70      - 16
71      - 64
72      - 128
73      - 256
74      - 512
75
76  d1ppre:
77    type: int
78    required: true
79    description: |
80        D1 domain, APB3 peripheral prescaler
81    enum:
82      - 1
83      - 2
84      - 4
85      - 8
86      - 16
87
88  d2ppre1:
89    type: int
90    required: true
91    description: |
92        D2 domain, APB1 peripheral prescaler
93    enum:
94      - 1
95      - 2
96      - 4
97      - 8
98      - 16
99
100  d2ppre2:
101    type: int
102    required: true
103    description: |
104        D2 domain, APB2 peripheral prescaler
105    enum:
106      - 1
107      - 2
108      - 4
109      - 8
110      - 16
111
112  d3ppre:
113    type: int
114    required: true
115    description: |
116        D3 domain, APB4 peripheral prescaler
117    enum:
118      - 1
119      - 2
120      - 4
121      - 8
122      - 16
123
124clock-cells:
125  - bus
126  - bits
127